drivers/generic/ioapic: Drop poor implementation

This disables MP table generation for the affected boards
since interrupt routing entries would now be completely missing.

The mechanism itself is flawed and redundant. The mapping
of integrated PCI devices' INTx pins to IOAPIC pins is
dependent of configuration registers and needs not appear
in the devicetree.cb files at all.

The write_smp_table implementation would skip writing
any entry delivering to destination IOAPIC ID 0. This
does not follow MP table specification.

There were duplicate calls to register_new_ioapic_gsi0(),
with another present under southbridge LPC device.

Change-Id: I383d55ba2bc0800423617215e0bfdfad5136e9ac
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69488
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

1 files changed, 0 insertions, 18 deletions

diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb
index 670b4883f33d..57f1f3753c0a 100644
--- a/src/mainboard/lenovo/t400/devicetree.cb
+++ b/src/mainboard/lenovo/t400/devicetree.cb
@@ -34,7 +34,6 @@ chip northbridge/intel/gm45
 		device pci 01.0 on end # PCIe Bridge for discrete graphics
 		device pci 02.0 on # VGA
 			subsystemid 0x17aa 0x20e4
-			ioapic_irq 2 INTA 0x10
 		end
 		device pci 02.1 on
 			subsystemid 0x17aa 0x20e4
@@ -85,27 +84,21 @@ chip northbridge/intel/gm45
 			device pci 19.0 on end # LAN
 			device pci 1a.0 on # UHCI
 				subsystemid 0x17aa 0x20f0
-				ioapic_irq 2 INTA 0x10
 			end
 			device pci 1a.1 on # UHCI
 				subsystemid 0x17aa 0x20f0
-				ioapic_irq 2 INTB 0x11
 			end
 			device pci 1a.2 on # UHCI
 				subsystemid 0x17aa 0x20f0
-				ioapic_irq 2 INTC 0x12
 			end
 			device pci 1a.7 on # EHCI
 				subsystemid 0x17aa 0x20f1
-				ioapic_irq 2 INTC 0x12
 			end
 			device pci 1b.0 on # HD Audio
 				subsystemid 0x17aa 0x20f2
-				ioapic_irq 2 INTA 0x10
 			end
 			device pci 1c.0 on # PCIe Port #1
 				subsystemid 0x17aa 0x20f3 # WWAN
-				ioapic_irq 2 INTA 0x10
 			end
 			device pci 1c.1 on
 				subsystemid 0x17aa 0x20f3 # WLAN
@@ -121,19 +114,15 @@ chip northbridge/intel/gm45
 			device pci 1c.5 off end # PCIe Port #6
 			device pci 1d.0 on # UHCI
 				subsystemid 0x17aa 0x20f0
-				ioapic_irq 2 INTA 0x10
 			end
 			device pci 1d.1 on # UHCI
 				subsystemid 0x17aa 0x20f0
-				ioapic_irq 2 INTB 0x11
 			end
 			device pci 1d.2 on # UHCI
 				subsystemid 0x17aa 0x20f0
-				ioapic_irq 2 INTC 0x12
 			end
 			device pci 1d.7 on # EHCI
 				subsystemid 0x17aa 0x20f1
-				ioapic_irq 2 INTA 0x10
 			end
 			device pci 1e.0 on # PCI
 				subsystemid 0x17aa 0x20f4
@@ -141,12 +130,6 @@ chip northbridge/intel/gm45
 			device pci 1f.0 on # LPC bridge
 				subsystemid 0x17aa 0x20f5
 
-				chip drivers/generic/ioapic
-					register "have_isa_interrupts" = "1"
-					register "base" = "(void *)0xfec00000"
-					device ioapic 2 on end
-				end
-
 				chip ec/lenovo/pmh7
 					device pnp ff.1 on end # dummy
 					register "backlight_enable" = "0x01"
@@ -217,7 +200,6 @@ chip northbridge/intel/gm45
 			end
 			device pci 1f.2 on # SATA/IDE 1
 				subsystemid 0x17aa 0x20f8
-				ioapic_irq 2 INTB 0x11
 			end
 			device pci 1f.3 on end	# SMBus
 			device pci 1f.5 off end # SATA/IDE 2