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| author | Keith Hui <buurin@gmail.com> | 2023-07-22 12:49:05 -0400 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-11-13 20:31:23 +0000 |
| commit | 45e4ab4a660cb7ce312f2d11a153f2d9ef4158da (patch) | |
| tree | 8b0fb3b07ecb3cfa84aa77b51c0e1053a1415c73 /src/mainboard/lenovo/t530 | |
| parent | 940fe080bf1ed2dac827b569c70fb0ea11496041 (diff) | |
| download | coreboot-45e4ab4a660cb7ce312f2d11a153f2d9ef4158da.tar.gz coreboot-45e4ab4a660cb7ce312f2d11a153f2d9ef4158da.tar.bz2 coreboot-45e4ab4a660cb7ce312f2d11a153f2d9ef4158da.zip | |
mb/*: Update SPD mapping for sandybridge boards
Boards without HAVE_SPD_IN_CBFS: Move SPD mapping into devicetree.
Boards with HAVE_SPD_IN_CBFS: Convert to Haswell-style SPD mapping.
Change-Id: Id6ac0a36b2fc0b9686f6e875dd020ae8dba72a72
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Diffstat (limited to 'src/mainboard/lenovo/t530')
4 files changed, 2 insertions, 16 deletions
diff --git a/src/mainboard/lenovo/t530/variants/t530/overridetree.cb b/src/mainboard/lenovo/t530/variants/t530/overridetree.cb index 78f7b9b34cca..98551ac96888 100644 --- a/src/mainboard/lenovo/t530/variants/t530/overridetree.cb +++ b/src/mainboard/lenovo/t530/variants/t530/overridetree.cb @@ -1,4 +1,5 @@ chip northbridge/intel/sandybridge + register "spd_addresses" = "{0x50, 0, 0x51, 0}" device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH device pci 1f.0 on # PCI-LPC bridge diff --git a/src/mainboard/lenovo/t530/variants/t530/romstage.c b/src/mainboard/lenovo/t530/variants/t530/romstage.c index 22bf0764aabe..2290bcea13d9 100644 --- a/src/mainboard/lenovo/t530/variants/t530/romstage.c +++ b/src/mainboard/lenovo/t530/variants/t530/romstage.c @@ -1,14 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x51, id_only); -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, /* P0: USB double port upper, USB3, OC 0 */ { 1, 1, 1 }, /* P1: USB double port lower, USB3, (EHCI debug) OC 1 */ diff --git a/src/mainboard/lenovo/t530/variants/w530/overridetree.cb b/src/mainboard/lenovo/t530/variants/w530/overridetree.cb index 115bc1f12abd..77b75fd23772 100644 --- a/src/mainboard/lenovo/t530/variants/w530/overridetree.cb +++ b/src/mainboard/lenovo/t530/variants/w530/overridetree.cb @@ -1,4 +1,5 @@ chip northbridge/intel/sandybridge + register "spd_addresses" = "{0x50, 0x52, 0x51, 0x53}" device domain 0 on device pci 02.0 on # Internal graphics VGA controller subsystemid 0x17aa 0x21f5 diff --git a/src/mainboard/lenovo/t530/variants/w530/romstage.c b/src/mainboard/lenovo/t530/variants/w530/romstage.c index f3ccc1426605..7458d1ad4de7 100644 --- a/src/mainboard/lenovo/t530/variants/w530/romstage.c +++ b/src/mainboard/lenovo/t530/variants/w530/romstage.c @@ -1,16 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[1], 0x52, id_only); - read_spd(&spd[2], 0x51, id_only); - read_spd(&spd[3], 0x53, id_only); -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, /* P0: USB double port upper, USB3, OC 0 */ { 1, 1, 1 }, /* P1: USB double port lower, USB3, (EHCI debug) OC 1 */ |