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| author | Sven Schnelle <svens@stackframe.org> | 2011-10-15 17:31:01 +0200 |
|---|---|---|
| committer | Sven Schnelle <svens@stackframe.org> | 2011-10-20 16:06:35 +0200 |
| commit | b5381105325391553b17c6ec2455233fc27e73b8 (patch) | |
| tree | 244f77d68819d0cd504ac3ac2ec47d56fb78c349 /src/mainboard/lenovo/t60/mainboard.c | |
| parent | 2588db496d8037c9e548a9dd75360a3785b0ae7f (diff) | |
| download | coreboot-b5381105325391553b17c6ec2455233fc27e73b8.tar.gz coreboot-b5381105325391553b17c6ec2455233fc27e73b8.tar.bz2 coreboot-b5381105325391553b17c6ec2455233fc27e73b8.zip | |
T60: Add support for Ultrabay Legacy I/O devices (40Y8122)
Those modules have basically the same Super I/O capabilities as
the Docking station. Unfortunately, the Super I/O in the module
shares the same I/O address as the Docking station, so we're not
allowed to connect the LPC Docking Bus if such a module is present.
To be able to detect this device and use it as early console for
coreboot, we have to initialize the GPIO Controller before, as
this device is detected via GPIO06.
Change-Id: If7c38bb6797f76cf28f09f3614ab9a33878571fb
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/282
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/lenovo/t60/mainboard.c')
| -rw-r--r-- | src/mainboard/lenovo/t60/mainboard.c | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index 2b8c5fe4b12f..8456992044e4 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -38,6 +38,7 @@ static void mainboard_enable(device_t dev) { + struct southbridge_intel_i82801gx_config *config; device_t dev0, idedev; u8 defaults_loaded = 0; @@ -50,8 +51,14 @@ static void mainboard_enable(device_t dev) ec_write(0x0c, 0xc7); idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1)); - if (idedev && idedev->chip_info && h8_ultrabay_device_present()) { - struct southbridge_intel_i82801gx_config *config = idedev->chip_info; + + if (!(inb(DEFAULT_GPIOBASE + 0x0c) & 0x40)) { + /* legacy I/O connected */ + pmh7_ultrabay_power_enable(1); + ec_write(0x0c, 0x84); + } else if (idedev && idedev->chip_info && + h8_ultrabay_device_present()) { + config = idedev->chip_info; config->ide_enable_primary = 1; pmh7_ultrabay_power_enable(1); ec_write(0x0c, 0x84); |