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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-03-23 10:07:16 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-03-24 10:40:40 +0000 |
| commit | 346d201d73d51ae0a037f64b1bc6d530745b5d4a (patch) | |
| tree | a6409d052902e76c4a87a9e34837c18a945fccb9 /src/mainboard/lenovo/x60/romstage.c | |
| parent | cf32fd172928467ac5bbd4fb372b71230c81cf12 (diff) | |
| download | coreboot-346d201d73d51ae0a037f64b1bc6d530745b5d4a.tar.gz coreboot-346d201d73d51ae0a037f64b1bc6d530745b5d4a.tar.bz2 coreboot-346d201d73d51ae0a037f64b1bc6d530745b5d4a.zip | |
nb/intel/i945: Use DEBUG_RAM_SETUP
Avoid preprocessor here, also we never set loglevel
to value of >8 so the call would not be made.
The calls to ram_check() were removed, for a long
time that function has not tested start..stop region.
Change-Id: Ib952b8905c29a5c5c289027071eb6ff59aaa330b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/lenovo/x60/romstage.c')
| -rw-r--r-- | src/mainboard/lenovo/x60/romstage.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 39e0ed57ac6a..e655ddf0e025 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -211,9 +211,8 @@ void mainboard_romstage_entry(unsigned long bist) /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif + if (CONFIG(DEBUG_RAM_SETUP)) + dump_spd_registers(); sdram_initialize(s3resume ? 2 : 0, spd_addrmap); |