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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-08-15 20:59:09 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2018-01-14 21:43:25 +0000 |
| commit | b451df2f400ba12fff440247330f8b57a93034bd (patch) | |
| tree | 8bb52821a42aaaea2e614910d97b1ae4e690b7c2 /src/mainboard/lenovo/z61t/romstage.c | |
| parent | e4a016ff17b455a8acd0ea72b30caabb622ce224 (diff) | |
| download | coreboot-b451df2f400ba12fff440247330f8b57a93034bd.tar.gz coreboot-b451df2f400ba12fff440247330f8b57a93034bd.tar.bz2 coreboot-b451df2f400ba12fff440247330f8b57a93034bd.zip | |
mb/*/*/romstage.c: Clean up targets with i82801gx
Things cleaned up in this patch:
* Add macros for the GENx_DEC registers;
* replace many magic numbers by macros;
* remove many writes to DxxIP since they were 'setting' reset default
values;
* fix some comments about decode ranges.
Change-Id: I9d6a0ff3d391947f611a2f3c65684f4ee57bc263
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/lenovo/z61t/romstage.c')
| -rw-r--r-- | src/mainboard/lenovo/z61t/romstage.c | 17 |
1 files changed, 8 insertions, 9 deletions
diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index 0b04f863fc30..ffb72e3af192 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -45,19 +45,18 @@ static void ich7_enable_lpc(void) // decode range pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210); // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, 0x1f0d); + pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN + | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN + | FDD_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); /* range 0x1600 - 0x167f */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x1601); - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x007c); + pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x007c1601); - /* range 0x15e0 - 0x10ef */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x15e1); - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x000c); + /* range 0x15e0 - 0x15ef */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000c15e1); /* range 0x1680 - 0x169f */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8c, 0x1681); - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8e, 0x001c); + pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x001c1681); } static void early_superio_config(void) @@ -146,7 +145,7 @@ static void early_ich7_init(void) RCBA32(0x0214) = 0x10030549; RCBA32(0x0218) = 0x00020504; RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(0x3410); + reg32 = RCBA32(GCS); reg32 |= (1 << 6); RCBA32(GCS) = reg32; reg32 = RCBA32(0x3430); |