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| author | Evgeny Zinoviev <me@ch1p.io> | 2021-11-22 02:51:14 +0300 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-11-23 16:57:14 +0000 |
| commit | 72628fa813231cb5af6a5aa373e184d2fd8a9509 (patch) | |
| tree | ca4560d855178b1ac8d25ee938e683d4b0042fad /src/mainboard/lenovo | |
| parent | b207f3f3708ac9d60841886814448a475fbdc39a (diff) | |
| download | coreboot-72628fa813231cb5af6a5aa373e184d2fd8a9509.tar.gz coreboot-72628fa813231cb5af6a5aa373e184d2fd8a9509.tar.bz2 coreboot-72628fa813231cb5af6a5aa373e184d2fd8a9509.zip | |
mb/lenovo: Enable MEI on Sandy Bridge ThinkPads
It was already enabled on T520 and L520, but disabled on X220, T420 and
T420s.
On X220, it was disabled by commit 0793afe9 (mb/lenovo/x220: disable ME).
I can't reproduce those issues today on linux 4.4 and linux 5.13.
Also, it breaks the me_disable feature, we already have a Kconfig option
to hide MEI in case of errors, and it will be hidden on disabled,
recovery, firmware update paths anyway.
Change-Id: I8e6d067a9c728443d00df541ac7a9a878df58b6a
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Diffstat (limited to 'src/mainboard/lenovo')
| -rw-r--r-- | src/mainboard/lenovo/t420/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/lenovo/t420s/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x220/devicetree.cb | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index e42e519f87b2..457ccbee1bee 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -61,7 +61,7 @@ chip northbridge/intel/sandybridge register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index ab98ca0bd0b6..32736a83f2c8 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -63,7 +63,7 @@ chip northbridge/intel/sandybridge register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 53eb23a1bd51..b239d64daec4 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -60,7 +60,7 @@ chip northbridge/intel/sandybridge register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT |