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| author | Furquan Shaikh <furquan@chromium.org> | 2017-03-31 14:02:47 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2017-04-06 00:45:36 +0200 |
| commit | 05a6f29d32c246569b7a0561d35ccbf49eec1fb8 (patch) | |
| tree | a0347e4edb13a2f3bebcbbf8745a4af0a5f18969 /src/mainboard/lowrisc | |
| parent | 108f87262bf47ce3549fa0c5ed16a40fe916656f (diff) | |
| download | coreboot-05a6f29d32c246569b7a0561d35ccbf49eec1fb8.tar.gz coreboot-05a6f29d32c246569b7a0561d35ccbf49eec1fb8.tar.bz2 coreboot-05a6f29d32c246569b7a0561d35ccbf49eec1fb8.zip | |
soc/intel/skylake: Add support for GSPI controller
Sky Lake PCH contains two GSPI controllers. Using the common GSPI
controller driver implementation for Intel PCH, add support for GSPI
controller buses on Sky Lake/Kaby Lake.
BUG=b:35583330
Change-Id: I29b1d4d5a6ee4093f2596065ac375c06f17d33ac
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19099
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/lowrisc')
0 files changed, 0 insertions, 0 deletions