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| author | Angel Pons <th3fanbus@gmail.com> | 2021-03-12 20:48:53 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-23 10:59:26 +0000 |
| commit | c4ee714881c7f7bb7a9208b39c76d98578c434b1 (patch) | |
| tree | bbf6051210754cd954b792163d2331eb0bf309bc /src/mainboard/msi/h81m-p33 | |
| parent | d99b693c965abb13aa57c5701bfd08547fa93cb5 (diff) | |
| download | coreboot-c4ee714881c7f7bb7a9208b39c76d98578c434b1.tar.gz coreboot-c4ee714881c7f7bb7a9208b39c76d98578c434b1.tar.bz2 coreboot-c4ee714881c7f7bb7a9208b39c76d98578c434b1.zip | |
nb/intel/haswell: Use unshifted SPD addresses in mainboards
It's common to use the raw, unshifted I2C address in coreboot. Adapt
mainboards accordingly and perform the shift in MRC glue code.
Tested on Asrock B85M Pro4, still boots and still resumes from S3.
Change-Id: I4e4978772744ea27f4c5a88def60a8ded66520e1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51458
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/msi/h81m-p33')
| -rw-r--r-- | src/mainboard/msi/h81m-p33/romstage.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/msi/h81m-p33/romstage.c b/src/mainboard/msi/h81m-p33/romstage.c index 059ebdc1b66d..97c888d9e763 100644 --- a/src/mainboard/msi/h81m-p33/romstage.c +++ b/src/mainboard/msi/h81m-p33/romstage.c @@ -19,8 +19,8 @@ void mainboard_config_rcba(void) void mb_get_spd_map(struct spd_info *spdi) { - spdi->addresses[0] = 0xa0; - spdi->addresses[2] = 0xa4; + spdi->addresses[0] = 0x50; + spdi->addresses[2] = 0x52; } const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { |