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| author | Johnny Lin <johnny_lin@wiwynn.com> | 2020-08-11 10:35:39 +0800 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-08-28 17:45:24 +0000 |
| commit | 6da1710fbc2a1795d879e16822523c22b372afe1 (patch) | |
| tree | 78b3cf70b35bbfae14f0be6828c5a44de800a2ac /src/mainboard/ocp/deltalake/romstage.c | |
| parent | d5f24dd99bb245a6de2d8ca86bfabda05bdb82d1 (diff) | |
| download | coreboot-6da1710fbc2a1795d879e16822523c22b372afe1.tar.gz coreboot-6da1710fbc2a1795d879e16822523c22b372afe1.tar.bz2 coreboot-6da1710fbc2a1795d879e16822523c22b372afe1.zip | |
mb/ocp/deltalake: Configure FSP DCI via VPD
Tested on OCP Delta Lake, with FSP WW34 DCI can be connected if enabled.
Change-Id: I8e0dff921cef02dfc66467a2b8fa3e196fb36ac2
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/ocp/deltalake/romstage.c')
| -rw-r--r-- | src/mainboard/ocp/deltalake/romstage.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c index f69ec60c7344..71a26c878954 100644 --- a/src/mainboard/ocp/deltalake/romstage.c +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -49,6 +49,16 @@ static void mainboard_config_upd(FSPM_UPD *mupd) mupd->FspmConfig.DebugPrintLevel = FSP_LOG_LEVEL_DEFAULT; } } + + /* Enable DCI */ + if (vpd_get_bool(FSP_DCI, VPD_RW_THEN_RO, &val)) { + printk(BIOS_DEBUG, "Setting DciEn %d from VPD\n", val); + mupd->FspmConfig.PchDciEn = val; + } else { + printk(BIOS_INFO, "Not able to get VPD %s, default set " + "DciEn to %d\n", FSP_DCI, FSP_DCI_DEFAULT); + mupd->FspmConfig.PchDciEn = FSP_DCI_DEFAULT; + } } /* Update bifurcation settings according to different Configs */ |