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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2018-12-17 12:25:50 +0100 |
|---|---|---|
| committer | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2018-12-19 15:38:29 +0000 |
| commit | 817994c1bec48733679c34fe717a07ad81af18ac (patch) | |
| tree | 003cc3eaff0d360a3b8242a61494e2af6086bf9b /src/mainboard/ocp | |
| parent | 990c84db9d0d4ce1968164d2fcc642a0e2554b68 (diff) | |
| download | coreboot-817994c1bec48733679c34fe717a07ad81af18ac.tar.gz coreboot-817994c1bec48733679c34fe717a07ad81af18ac.tar.bz2 coreboot-817994c1bec48733679c34fe717a07ad81af18ac.zip | |
mb/ocp/wedge100s/romstage: Workaround broken platform state
Sometimes the platform boots in an invalid state, that will cause
FSP-M to fail. As a board_reset() doesn't fix it, issue an full_reset()
as soon as the IA32_FEATURE_CONTROL MSR is locked at beging of romstage.
Tested on wedge100s. After full reset the system behaves as normal.
Change-Id: I1a382b8fb650311b0c24b48e0986d22edfa2d261
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Diffstat (limited to 'src/mainboard/ocp')
| -rw-r--r-- | src/mainboard/ocp/wedge100s/romstage.c | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/src/mainboard/ocp/wedge100s/romstage.c b/src/mainboard/ocp/wedge100s/romstage.c index cf52c01f0466..1d770366ba99 100644 --- a/src/mainboard/ocp/wedge100s/romstage.c +++ b/src/mainboard/ocp/wedge100s/romstage.c @@ -17,6 +17,9 @@ #include <stddef.h> #include <soc/romstage.h> #include <drivers/intel/fsp1_0/fsp_util.h> +#include <cpu/x86/msr.h> +#include <cf9_reset.h> +#include <console/console.h> /** * /brief mainboard call for setup that needs to be done before fsp init @@ -24,7 +27,22 @@ */ void early_mainboard_romstage_entry(void) { - + /* + * Sometimes the system boots in an invalid state, where random values + * have been written to MSRs and then the MSRs are locked. + * Seems to always happen on warm reset. + * + * Power cycling or a board_reset() isn't sufficient in this case, so + * issue a full_reset() to "fix" this issue. + * + * It seems to be a deficiency in the reset logic, as other + * FSP broadwell DE boards are not affected. + */ + msr_t msr = rdmsr(IA32_FEATURE_CONTROL); + if (msr.lo & 1) { + printk(BIOS_EMERG, "Detected broken platform state. Issuing full reset\n"); + full_reset(); + } } /** |