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| author | Martin Roth <martin@coreboot.org> | 2020-06-17 13:44:59 -0600 |
|---|---|---|
| committer | Michał Żygowski <michal.zygowski@3mdeb.com> | 2020-06-19 09:38:59 +0000 |
| commit | 87f9fc8584c980dc4c73667f4c88d71d0e447a0c (patch) | |
| tree | 8d5377c4610456b90c21f9f119c6484357cb3703 /src/mainboard/pcengines/apu2/gpio_ftns.c | |
| parent | 4cb2f7684e6ec746d7de1b51f9c86935f9d3d64f (diff) | |
| download | coreboot-87f9fc8584c980dc4c73667f4c88d71d0e447a0c.tar.gz coreboot-87f9fc8584c980dc4c73667f4c88d71d0e447a0c.tar.bz2 coreboot-87f9fc8584c980dc4c73667f4c88d71d0e447a0c.zip | |
mb/pcengines/apu2: Update GPIO Reads & writes
The APU2 was using the soc/amd/common functions to do GPIO reads and
writes. The functions that were being used are getting eliminated in
the SOC directory, but since the APU isn't using the rest of that code
(as it's not using the rest of the SOC codebase), it proved to be
problematic to use the updated functions.
The solution I've put in place here is to pull everything needed for the
GPIO reads & writes into the gpio_ftns.c & h files.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ied39c114bdf3637977d21f56fd7db428c52e4706
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Diffstat (limited to 'src/mainboard/pcengines/apu2/gpio_ftns.c')
| -rw-r--r-- | src/mainboard/pcengines/apu2/gpio_ftns.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.c b/src/mainboard/pcengines/apu2/gpio_ftns.c index c249c2da5ca7..7bf0bc9a533c 100644 --- a/src/mainboard/pcengines/apu2/gpio_ftns.c +++ b/src/mainboard/pcengines/apu2/gpio_ftns.c @@ -12,11 +12,11 @@ static u32 gpio_read_wrapper(u32 iomux_gpio) u32 gpio = iomux_gpio << 2; if (gpio < 0x100) - return gpio0_read32(gpio & 0xff); + return read32((void *)(ACPIMMIO_GPIO0_BASE + (gpio & 0xff))); else if (gpio >= 0x100 && gpio < 0x200) - return gpio1_read32(gpio & 0xff); + return read32((void *)(ACPIMMIO_GPIO1_BASE + (gpio & 0xff))); else if (gpio >= 0x200 && gpio < 0x300) - return gpio2_read32(gpio & 0xff); + return read32((void *)(ACPIMMIO_GPIO2_BASE + (gpio & 0xff))); die("Invalid GPIO"); } @@ -26,11 +26,11 @@ static void gpio_write_wrapper(u32 iomux_gpio, u32 setting) u32 gpio = iomux_gpio << 2; if (gpio < 0x100) - gpio0_write32(gpio & 0xff, setting); + write32((void *)(ACPIMMIO_GPIO0_BASE + (gpio & 0xff)), setting); else if (gpio >= 0x100 && gpio < 0x200) - gpio1_write32(gpio & 0xff, setting); + write32((void *)(ACPIMMIO_GPIO1_BASE + (gpio & 0xff)), setting); else if (gpio >= 0x200 && gpio < 0x300) - gpio2_write32(gpio & 0xff, setting); + write32((void *)(ACPIMMIO_GPIO2_BASE + (gpio & 0xff)), setting); } void configure_gpio(u32 gpio, u8 iomux_ftn, u32 setting) @@ -70,9 +70,9 @@ int get_spd_offset(void) * One SPD file contains all 4 options, determine which index to * read here, then call into the standard routines. */ - if (gpio1_read8(0x02) & BIT0) + if (read32((void *)(ACPIMMIO_GPIO1_BASE + 0x02)) & BIT0) index |= BIT0; - if (gpio1_read8(0x06) & BIT0) + if (read32((void *)(ACPIMMIO_GPIO1_BASE + 0x06)) & BIT0) index |= BIT1; return index; |