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| author | Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com> | 2020-01-08 16:09:59 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-01-20 11:10:20 +0000 |
| commit | 302951d9c3eb812a42cb6560a5d2b0096fbe85d5 (patch) | |
| tree | 5f5882be22a5e4dfe9fe6ca3e75d909bfb8529c7 /src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb | |
| parent | 79d7f6b5fc62964e8c935b044a434ee112160059 (diff) | |
| download | coreboot-302951d9c3eb812a42cb6560a5d2b0096fbe85d5.tar.gz coreboot-302951d9c3eb812a42cb6560a5d2b0096fbe85d5.tar.bz2 coreboot-302951d9c3eb812a42cb6560a5d2b0096fbe85d5.zip | |
mb/pcengines/*: enable simple IO-based GPIO control
Add Nuvoton NCT5104D GPIO IO VLDN and define an IO base address
unused by any peripheral for GPIO use.
Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I034c5d0169b8d97eac97a20c92c22816fd674f79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb')
| -rw-r--r-- | src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb index ad299657f1b8..524f30f3d89d 100644 --- a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb @@ -64,7 +64,10 @@ chip northbridge/amd/pi/00730F01/root_complex io 0x60 = 0x2e8 irq 0x70 = 3 end - device pnp 2e.8 off end + device pnp 2e.008 off end + device pnp 2e.108 on + io 0x60 = 0x220 + end # GPIO0 and GPIO1 are conditionally turned on device pnp 2e.007 on end device pnp 2e.107 on end |