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| author | Felix Singer <felixsinger@posteo.net> | 2020-07-29 22:28:37 +0200 |
|---|---|---|
| committer | Michael Niewöhner <c0d3z3r0@review.coreboot.org> | 2020-08-08 12:01:18 +0000 |
| commit | 4d5c4e069cb99e715d04bf238e406a008f16707d (patch) | |
| tree | 5614365c7b55999717ea40ff9c0de809830915d0 /src/mainboard/protectli/vault_kbl/devicetree.cb | |
| parent | 88264ef30bcb20e8dd56de22cf564ebadd0bc2e9 (diff) | |
| download | coreboot-4d5c4e069cb99e715d04bf238e406a008f16707d.tar.gz coreboot-4d5c4e069cb99e715d04bf238e406a008f16707d.tar.bz2 coreboot-4d5c4e069cb99e715d04bf238e406a008f16707d.zip | |
soc/intel/skylake: Enable SA IMGU depending on devicetree configuration
Currently, SA IMGU gets enabled by the option SaImguEnable,
but this duplicates the devicetree on/off options. Therefore, depend on
the devicetree for the enablement of the SA IMGU controller.
All corresponding mainboards were checked if the devicetree
configuration matches the SaImguEnable setting, and missing entries
were added.
Change-Id: I293a20a321c75f82a57cbd5339656d93509b7aa6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Diffstat (limited to 'src/mainboard/protectli/vault_kbl/devicetree.cb')
| -rw-r--r-- | src/mainboard/protectli/vault_kbl/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 63861c616fe8..f0759efa9027 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -45,7 +45,6 @@ chip soc/intel/skylake register "HeciEnabled" = "1" register "PmTimerDisabled" = "1" register "SaGv" = "SaGv_Enabled" - register "SaImguEnable" = "0" register "IslVrCmd" = "2" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "4" # 4s @@ -218,6 +217,7 @@ chip soc/intel/skylake device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device device pci 04.0 off end # SA thermal subsystem + device pci 05.0 off end # SA IMGU device pci 08.0 off end # Gaussian Mixture Model device pci 13.0 off end # Integrated Sensor Hub device pci 14.0 on end # USB xHCI |