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| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-10-15 00:36:29 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-10-26 06:51:42 +0000 |
| commit | a64b4f454894988a9c043d53d00b493852f261a3 (patch) | |
| tree | 44aacf270999724b4461edb3b4c35959482b4330 /src/mainboard/protectli/vault_kbl/devicetree.cb | |
| parent | d5a45470c816bc8a8bdc43951c9e4c4a592b55d3 (diff) | |
| download | coreboot-a64b4f454894988a9c043d53d00b493852f261a3.tar.gz coreboot-a64b4f454894988a9c043d53d00b493852f261a3.tar.bz2 coreboot-a64b4f454894988a9c043d53d00b493852f261a3.zip | |
mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`
The dt option `speed_shift_enable` is obsolete now. Drop it.
Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Diffstat (limited to 'src/mainboard/protectli/vault_kbl/devicetree.cb')
| -rw-r--r-- | src/mainboard/protectli/vault_kbl/devicetree.cb | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 2a4b1e9ffd85..e6e748a2476e 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -17,8 +17,6 @@ chip soc/intel/skylake register "gen3_dec" = "0x000c03e1" register "gen4_dec" = "0x001c02e1" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" register "eist_enable" = "1" # Disable DPTF |