mb/purism/librem_whl: rename to librem_cnl

Since Whiskeylake SoC code is actually a subset of soc/intel/cannonlake,
rename the baseboard so that boards using other 'cannonlake family' SoCs
(e.g., Cometlake) can be added with minimal confusion.

Rename the mainboard dir and baseboard name, and adjust any references
to them.

Change-Id: I2af7977f1622070eb8bf8449bc8306f9d75b9851
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

1 files changed, 791 insertions, 0 deletions

diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c
new file mode 100644
index 000000000000..254510ead516
--- /dev/null
+++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c
@@ -0,0 +1,791 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <variant/gpio.h>
+
+/* Pad configuration was generated automatically using intelp2m utility */
+static const struct pad_config gpio_table[] = {
+
+	/* ------- GPIO Community 0 ------- */
+
+	/* ------- GPIO Group GPP_A ------- */
+
+	/* GPP_A0 - RCIN# */
+	/* DW0: 0x44000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
+
+	/* GPP_A1 - LAD0 */
+	/* DW0: 0x44000702, DW1: 0x00003c00 */
+	PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
+
+	/* GPP_A2 - LAD1 */
+	/* DW0: 0x44000702, DW1: 0x00003c00 */
+	PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
+
+	/* GPP_A3 - LAD2 */
+	/* DW0: 0x44000702, DW1: 0x00003c00 */
+	PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
+
+	/* GPP_A4 - LAD3 */
+	/* DW0: 0x44000702, DW1: 0x00003c00 */
+	PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
+
+	/* GPP_A5 - LFRAME# */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
+
+	/* GPP_A6 - SERIRQ */
+	/* DW0: 0x44000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+
+	/* GPP_A7 - GPIO */
+	/* DW0: 0x44000200, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_A7, 0, DEEP),
+
+	/* GPP_A8 - CLKRUN# */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
+
+	/* GPP_A9 - CLKOUT_LPC0 */
+	/* DW0: 0x44000700, DW1: 0x00001000 */
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
+
+	/* GPP_A10 - CLKOUT_LPC1 */
+	/* DW0: 0x44000700, DW1: 0x00001000 */
+	PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
+
+	/* GPP_A11 - GPIO */
+	/* DW0: 0x80880201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_A11, 1, PLTRST),
+
+	/* GPP_A12 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_A12, 1, PLTRST),
+
+	/* GPP_A13 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_A13, 1, PLTRST),
+
+	/* GPP_A14 - SUS_STAT# */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+
+	/* GPP_A15 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_A15, 1, PLTRST),
+
+	/* GPP_A16 - GPIO */
+	/* DW0: 0x84000200, DW1: 0x00003000 */
+	PAD_CFG_TERM_GPO(GPP_A16, 0, UP_20K, PLTRST),
+
+	/* GPP_A17 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_A17, 1, PLTRST),
+
+	/* GPP_A18 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00003000 */
+	PAD_NC(GPP_A18, UP_20K),
+
+	/* GPP_A19 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00003000 */
+	PAD_NC(GPP_A19, UP_20K),
+
+	/* GPP_A20 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00003000 */
+	PAD_NC(GPP_A20, UP_20K),
+
+	/* GPP_A21 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00003000 */
+	PAD_NC(GPP_A21, UP_20K),
+
+	/* GPP_A22 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00003000 */
+	PAD_NC(GPP_A22, UP_20K),
+
+	/* GPP_A23 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00003000 */
+	PAD_NC(GPP_A23, UP_20K),
+
+	/* ------- GPIO Group GPP_B ------- */
+
+	/* GPP_B0 - Reserved */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
+
+	/* GPP_B1 - Reserved */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
+
+	/* GPP_B2 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_B2, 1, PLTRST),
+
+	/* GPP_B3 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_B3, 1, PLTRST),
+
+	/* GPP_B4 - GPIO */
+	/* DW0: 0x44000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+
+	/* GPP_B5 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_B5, NONE),
+
+	/* GPP_B6 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_B6, NONE),
+
+	/* GPP_B7 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_B7, NONE),
+
+	/* GPP_B8 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_B8, NONE),
+
+	/* GPP_B9 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_B9, NONE),
+
+	/* GPP_B10 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_B10, NONE),
+
+	/* GPP_B11 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_B11, 1, PLTRST),
+
+	/* GPP_B12 - SLP_S0# */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+
+	/* GPP_B13 - PLTRST# */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+
+	/* GPP_B14 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_B14, 1, PLTRST),
+
+	/* GPP_B15 - GSPI0_CS0# */
+	/* DW0: 0x00000701, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_B15, NONE, PWROK, NF1),
+
+	/* GPP_B16 - GSPI0_CLK */
+	/* DW0: 0x84000601, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_B16, NONE, PLTRST, NF1),
+
+	/* GPP_B17 - GSPI0_MISO */
+	/* DW0: 0x44000502, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
+
+	/* GPP_B18 - GSPI0_MOSI */
+	/* DW0: 0x84000601, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_B18, NONE, PLTRST, NF1),
+
+	/* GPP_B19 - GSPI1_CS0# */
+	/* DW0: 0x84000400, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_B19, NONE, PLTRST, NF1),
+
+	/* GPP_B20 - GSPI1_CLK */
+	/* DW0: 0x84000400, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_B20, NONE, PLTRST, NF1),
+
+	/* GPP_B21 - GSPI1_MISO */
+	/* DW0: 0x84000402, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_B21, NONE, PLTRST, NF1),
+
+	/* GPP_B22 - GSPI1_MOSI */
+	/* DW0: 0x84000400, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_B22, NONE, PLTRST, NF1),
+
+	/* GPP_B23 - GPIO */
+	/* DW0: 0x44000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_B23, 1, DEEP),
+
+	/* ------- GPIO Group GPP_G ------- */
+
+	/* GPP_G0 - GPIO */
+	/* DW0: 0x04000200, DW1: 0x00001000 */
+	PAD_CFG_TERM_GPO(GPP_G0, 0, DN_20K, PWROK),
+
+	/* GPP_G1 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_G1, NONE),
+
+	/* GPP_G2 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_G2, NONE),
+
+	/* GPP_G3 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_G3, NONE),
+
+	/* GPP_G4 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_G4, NONE),
+
+	/* GPP_G5 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00003000 */
+	PAD_NC(GPP_G5, UP_20K),
+
+	/* GPP_G6 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_G6, NONE),
+
+	/* GPP_G7 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00001000 */
+	PAD_NC(GPP_G7, DN_20K),
+
+	/* ------- GPIO Community 1 ------- */
+
+	/* ------- GPIO Group GPP_D ------- */
+
+	/* GPP_D0 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_D0, NONE),
+
+	/* GPP_D1 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_D1, NONE),
+
+	/* GPP_D2 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_D2, NONE),
+
+	/* GPP_D3 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_D3, NONE),
+
+	/* GPP_D4 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_D4, NONE),
+
+	/* GPP_D5 - ISH_I2C0_SDA */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+
+	/* GPP_D6 - ISH_I2C0_SCL */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+
+	/* GPP_D7 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_D7, 1, PLTRST),
+
+	/* GPP_D8 - GPIO */
+	/* DW0: 0x84000200, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_D8, 0, PLTRST),
+
+	/* GPP_D9 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_D9, 1, PLTRST),
+
+	/* GPP_D10 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_D10, 1, PLTRST),
+
+	/* GPP_D11 - GPIO */
+	/* DW0: 0x44000201, DW1: 0x00003000 */
+	PAD_CFG_TERM_GPO(GPP_D11, 1, UP_20K, DEEP),
+
+	/* GPP_D12 - GPIO */
+	/* DW0: 0x42100102, DW1: 0x00003000 */
+	PAD_CFG_GPI_APIC(GPP_D12, UP_20K, DEEP, EDGE_SINGLE, NONE),
+
+	/* GPP_D13 - GPIO */
+	/* DW0: 0x04000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_D13, 1, RSMRST),
+
+	/* GPP_D14 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_D14, 1, PLTRST),
+
+	/* GPP_D15 - GPIO */
+	/* DW0: 0x44000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_D15, 1, DEEP),
+
+	/* GPP_D16 - GPIO */
+	/* DW0: 0x04000200, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_D16, 0, RSMRST),
+
+	/* GPP_D17 - DMIC_CLK1 */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+
+	/* GPP_D18 - DMIC_DATA1 */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+
+	/* GPP_D19 - DMIC_CLK0 */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+
+	/* GPP_D20 - DMIC_DATA0 */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+
+	/* GPP_D21 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_D21, NONE),
+
+	/* GPP_D22 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_D22, NONE),
+
+	/* GPP_D23 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_D23, NONE),
+
+	/* ------- GPIO Group GPP_F ------- */
+
+	/* GPP_F0 - GPIO */
+	/* DW0: 0x00000301, DW1: 0x00000000 */
+	PAD_NC(GPP_F0, NONE),
+
+	/* GPP_F1 - GPIO */
+	/* DW0: 0x04000200, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_F1, 0, RSMRST),
+
+	/* GPP_F2 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00003000 */
+	PAD_CFG_TERM_GPO(GPP_F2, 1, UP_20K, PLTRST),
+
+	/* GPP_F3 - GPIO */
+	/* DW0: 0x84000200, DW1: 0x00003000 */
+	PAD_CFG_TERM_GPO(GPP_F3, 0, UP_20K, PLTRST),
+
+	/* GPP_F4 - CNV_BRI_DT */
+	/* DW0: 0x44000700, DW1: 0x00003000 */
+	PAD_CFG_NF(GPP_F4, UP_20K, DEEP, NF1),
+
+	/* GPP_F5 - CNV_BRI_RSP */
+	/* DW0: 0x44000702, DW1: 0x00003000 */
+	PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1),
+
+	/* GPP_F6 - CNV_RGI_DT */
+	/* DW0: 0x44000700, DW1: 0x00003000 */
+	PAD_CFG_NF(GPP_F6, UP_20K, DEEP, NF1),
+
+	/* GPP_F7 - CNV_RGI_RSP */
+	/* DW0: 0x44000702, DW1: 0x00003000 */
+	PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1),
+
+	/* GPP_F8 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_F8, NONE),
+
+	/* GPP_F9 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_F9, NONE),
+
+	/* GPP_F10 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_F10, 1, PLTRST),
+
+	/* GPP_F11 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_F11, NONE),
+
+	/* GPP_F12 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_F12, NONE),
+
+	/* GPP_F13 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_F13, NONE),
+
+	/* GPP_F14 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_F14, NONE),
+
+	/* GPP_F15 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_F15, NONE),
+
+	/* GPP_F16 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_F16, NONE),
+
+	/* GPP_F17 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_F17, NONE),
+
+	/* GPP_F18 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_F18, NONE),
+
+	/* GPP_F19 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_F19, NONE),
+
+	/* GPP_F20 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_F20, NONE),
+
+	/* GPP_F21 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_F21, NONE),
+
+	/* GPP_F22 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_F22, NONE),
+
+	/* GPP_F23 - A4WP_PRESENT */
+	/* DW0: 0x44000700, DW1: 0x00001000 */
+	PAD_CFG_NF(GPP_F23, DN_20K, DEEP, NF1),
+
+	/* ------- GPIO Group GPP_H ------- */
+
+	/* GPP_H0 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00003000 */
+	PAD_NC(GPP_H0, UP_20K),
+
+	/* GPP_H1 - CNV_RF_RESET# */
+	/* DW0: 0x44000f00, DW1: 0x00003000 */
+	PAD_CFG_NF(GPP_H1, UP_20K, DEEP, NF3),
+
+	/* GPP_H2 - MODEM_CLKREQ */
+	/* DW0: 0x44000f00, DW1: 0x00003000 */
+	PAD_CFG_NF(GPP_H2, UP_20K, DEEP, NF3),
+
+	/* GPP_H3 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00003000 */
+	PAD_NC(GPP_H3, UP_20K),
+
+	/* GPP_H4 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_H4, NONE),
+
+	/* GPP_H5 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_H5, NONE),
+
+	/* GPP_H6 - I2C3_SDA */
+	/* DW0: 0x44000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+
+	/* GPP_H7 - I2C3_SCL */
+	/* DW0: 0x44000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+
+	/* GPP_H8 - I2C4_SDA */
+	/* DW0: 0x44000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
+
+	/* GPP_H9 - I2C4_SCL */
+	/* DW0: 0x44000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
+
+	/* GPP_H10 - I2C5_SDA */
+	/* DW0: 0x84000603, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF1),
+
+	/* GPP_H11 - I2C5_SCL */
+	/* DW0: 0x84000603, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF1),
+
+	/* GPP_H12 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_H12, 1, PLTRST),
+
+	/* GPP_H13 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_H13, 1, PLTRST),
+
+	/* GPP_H14 - GPIO */
+	/* DW0: 0x84000200, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_H14, 0, PLTRST),
+
+	/* GPP_H15 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_H15, 1, PLTRST),
+
+	/* GPP_H16 - GPIO */
+	/* DW0: 0x04000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_H16, 1, RSMRST),
+
+	/* GPP_H17 - GPIO */
+	/* DW0: 0x04000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_H17, 1, RSMRST),
+
+	/* GPP_H18 - CPU_C10_GATE# */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
+
+	/* GPP_H19 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_H19, 1, PLTRST),
+
+	/* GPP_H20 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_H20, NONE),
+
+	/* GPP_H21 - GPIO */
+	/* DW0: 0x44000200, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_H21, 0, DEEP),
+
+	/* GPP_H22 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_H22, 1, PLTRST),
+
+	/* GPP_H23 - GPIO */
+	/* DW0: 0x44000200, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_H23, 0, DEEP),
+
+	/* ------- GPIO Community 2 ------- */
+
+	/* ------- GPIO Group GPD ------- */
+
+	/* GPD0 - BATLOW# */
+	/* DW0: 0x04000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPD0, NONE, RSMRST, NF1),
+
+	/* GPD1 - ACPRESENT */
+	/* DW0: 0x04000702, DW1: 0x00003c00 */
+	PAD_CFG_NF(GPD1, NATIVE, RSMRST, NF1),
+
+	/* GPD2 - LAN_WAKE# */
+	/* DW0: 0x04000702, DW1: 0x00003c00 */
+	PAD_CFG_NF(GPD2, NATIVE, RSMRST, NF1),
+
+	/* GPD3 - PRWBTN# */
+	/* DW0: 0x04000702, DW1: 0x00003000 */
+	PAD_CFG_NF(GPD3, UP_20K, RSMRST, NF1),
+
+	/* GPD4 - SLP_S3# */
+	/* DW0: 0x04000600, DW1: 0x00000000 */
+	PAD_CFG_NF(GPD4, NONE, RSMRST, NF1),
+
+	/* GPD5 - SLP_S4# */
+	/* DW0: 0x04000600, DW1: 0x00000000 */
+	PAD_CFG_NF(GPD5, NONE, RSMRST, NF1),
+
+	/* GPD6 - SLP_A# */
+	/* DW0: 0x04000600, DW1: 0x00000000 */
+	PAD_CFG_NF(GPD6, NONE, RSMRST, NF1),
+
+	/* GPD7 - GPIO */
+	/* DW0: 0x04000200, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPD7, 0, RSMRST),
+
+	/* GPD8 - SUSCLK */
+	/* DW0: 0x04000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPD8, NONE, RSMRST, NF1),
+
+	/* GPD9 - SLP_WLAN# */
+	/* DW0: 0x04000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPD9, NONE, RSMRST, NF1),
+
+	/* GPD10 - SLP_S5# */
+	/* DW0: 0x04000600, DW1: 0x00000000 */
+	PAD_CFG_NF(GPD10, NONE, RSMRST, NF1),
+
+	/* GPD11 - LANPHYPC */
+	/* DW0: 0x04000600, DW1: 0x00000000 */
+	PAD_CFG_NF(GPD11, NONE, RSMRST, NF1),
+
+	/* ------- GPIO Community 4 ------- */
+
+	/* ------- GPIO Group GPP_C ------- */
+
+	/* GPP_C0 - SMBCLK */
+	/* DW0: 0x44000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+
+	/* GPP_C1 - SMBDATA */
+	/* DW0: 0x44000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+
+	/* GPP_C2 - GPIO */
+	/* DW0: 0x44000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_C2, 1, DEEP),
+
+	/* GPP_C3 - SML0CLK */
+	/* DW0: 0x44000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
+
+	/* GPP_C4 - SML0DATA */
+	/* DW0: 0x44000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
+
+	/* GPP_C5 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_C5, 1, PLTRST),
+
+	/* GPP_C6 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_C6, NONE),
+
+	/* GPP_C7 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_C7, NONE),
+
+	/* GPP_C8 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_C8, 1, PLTRST),
+
+	/* GPP_C9 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_C9, 1, PLTRST),
+
+	/* GPP_C10 - GPIO */
+	/* DW0: 0x84000200, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_C10, 0, PLTRST),
+
+	/* GPP_C11 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_C11, 1, PLTRST),
+
+	/* GPP_C12 - UART1_RXD */
+	/* DW0: 0x84000603, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_C12, NONE, PLTRST, NF1),
+
+	/* GPP_C13 - UART1_TXD */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
+
+	/* GPP_C14 - UART1_RTS# */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
+
+	/* GPP_C15 - UART1_CTS# */
+	/* DW0: 0x44000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1),
+
+	/* GPP_C16 - I2C0_SDA */
+	/* DW0: 0x84000402, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1),
+
+	/* GPP_C17 - I2C0_SCL */
+	/* DW0: 0x84000402, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1),
+
+	/* GPP_C18 - I2C1_SDA */
+	/* DW0: 0x44000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+
+	/* GPP_C19 - I2C1_SCL */
+	/* DW0: 0x44000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+
+	/* GPP_C20 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_C20, NONE),
+
+	/* GPP_C21 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_C21, NONE),
+
+	/* GPP_C22 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_C22, 1, PLTRST),
+
+	/* GPP_C23 - GPIO */
+	/* DW0: 0x40100102, DW1: 0x00001000 */
+	PAD_CFG_GPI_APIC(GPP_C23, DN_20K, DEEP, LEVEL, NONE),
+
+	/* ------- GPIO Group GPP_E ------- */
+
+	/* GPP_E0 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_E0, NONE),
+
+	/* GPP_E1 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_E1, NONE),
+
+	/* GPP_E2 - SATAXPCIE2 */
+	/* DW0: 0x84000502, DW1: 0x00003000 */
+	PAD_CFG_NF(GPP_E2, UP_20K, PLTRST, NF1),
+
+	/* GPP_E3 - GPIO */
+	/* DW0: 0x82040102, DW1: 0x00000000 */
+	PAD_CFG_GPI_SMI(GPP_E3, NONE, PLTRST, EDGE_SINGLE, NONE),
+
+	/* GPP_E4 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_E4, 1, PLTRST),
+
+	/* GPP_E5 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_E5, NONE),
+
+	/* GPP_E6 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_E6, NONE),
+
+	/* GPP_E7 - GPIO */
+	/* DW0: 0x82000102, DW1: 0x00000000 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, PLTRST, EDGE_SINGLE, ACPI),
+
+	/* GPP_E8 - SATALED# */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+
+	/* GPP_E9 - RESERVED */
+	/* DW0: 0x44001700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF5),
+
+	/* GPP_E10 - RESERVED */
+	/* DW0: 0x44001700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_E10, NONE, DEEP, NF5),
+
+	/* GPP_E11 - USB2_OC2# */
+	/* DW0: 0x44000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
+
+	/* GPP_E12 - USB2_OC3# */
+	/* DW0: 0x44000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
+
+	/* GPP_E13 - DDPB_HPD0 */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
+
+	/* GPP_E14 - DDPC_HPD1 */
+	/* DW0: 0x44000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+
+	/* GPP_E15 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_E15, 1, PLTRST),
+
+	/* GPP_E16 - GPIO */
+	/* DW0: 0x80880102, DW1: 0x00003000 */
+	PAD_CFG_GPI_SCI(GPP_E16, UP_20K, PLTRST, LEVEL, INVERT),
+
+	/* GPP_E17 - EDP_HPD */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
+
+	/* GPP_E18 - DPPB_CTRLCLK */
+	/* DW0: 0x44000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
+
+	/* GPP_E19 - DPPB_CTRLDATA */
+	/* DW0: 0x44000602, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
+
+	/* GPP_E20 - DPPC_CTRLCLK */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
+
+	/* GPP_E21 - DPPC_CTRLDATA */
+	/* DW0: 0x44000602, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+
+	/* GPP_E22 - DPPD_CTRLCLK */
+	/* DW0: 0x44000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1),
+
+	/* GPP_E23 - DPPD_CTRLDATA */
+	/* DW0: 0x44000602, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1),
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}