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| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-12-28 00:49:33 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2021-01-01 21:12:12 +0000 |
| commit | 97e21d3e956ea2657a63fb98c22548f9fd52afef (patch) | |
| tree | 8402f766ce761b557661ad57cc20bcb85694c0ea /src/mainboard/purism | |
| parent | 44fa0d4ca00fa4ca88415b7ca717767dd31f83f7 (diff) | |
| download | coreboot-97e21d3e956ea2657a63fb98c22548f9fd52afef.tar.gz coreboot-97e21d3e956ea2657a63fb98c22548f9fd52afef.tar.bz2 coreboot-97e21d3e956ea2657a63fb98c22548f9fd52afef.zip | |
nb/intel/hsw,soc/intel/{bdw,skl,apl},mb/*: unify dt panel settings
There are multiple different devicetree setting formats for graphics
panel settings present in coreboot. Replace the ones for the platforms
that already have (mostly) unified gma/graphics setup code by a unified
struct in the gma driver. Hook it up in HSW, BDW, SKL, and APL and adapt
the devicetrees accordingly.
Always ensure that values don't overflow by applying appropriate masks.
The remaining platforms implementing panel settings (GM45, i945, ILK and
SNB) can be migrated later after unifying their gma/graphics setup code.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I445defe01d5fbf9a69cf05cf1b5bd6c7c2c1725e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/purism')
| -rw-r--r-- | src/mainboard/purism/librem_bdw/devicetree.cb | 17 | ||||
| -rw-r--r-- | src/mainboard/purism/librem_skl/devicetree.cb | 17 |
2 files changed, 17 insertions, 17 deletions
diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb index 41943e72ef43..cd5bb44b7c7e 100644 --- a/src/mainboard/purism/librem_bdw/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/devicetree.cb @@ -6,15 +6,14 @@ chip soc/intel/broadwell # Enable DDI1 Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - # Set backlight PWM value for eDP - register "gpu_pch_backlight_pwm_hz" = "200" - - # Set panel power delays - register "gpu_panel_power_cycle_delay_ms" = "500" - register "gpu_panel_power_up_delay_ms" = "200" - register "gpu_panel_power_down_delay_ms" = "50" - register "gpu_panel_power_backlight_on_delay_ms" = "200" - register "gpu_panel_power_backlight_off_delay_ms" = "200" + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 200, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 200, + }" device cpu_cluster 0 on device lapic 0 on end diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index c59df4051871..c3a9567ccfe6 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -1,16 +1,17 @@ chip soc/intel/skylake - register "gpu_pp_up_delay_ms" = "200" - register "gpu_pp_down_delay_ms" = " 50" - register "gpu_pp_cycle_delay_ms" = "500" - register "gpu_pp_backlight_on_delay_ms" = " 1" - register "gpu_pp_backlight_off_delay_ms" = "200" - - register "gpu_pch_backlight_pwm_hz" = "200" - # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 200, + }" + register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "0" register "deep_s5_enable_ac" = "0" |