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| author | Angel Pons <th3fanbus@gmail.com> | 2021-08-29 18:27:09 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-08-31 15:13:29 +0000 |
| commit | ab11f462191263e56ac539d532a365699d88b8f3 (patch) | |
| tree | fee1853700f935391fbc71d55bb9b6373fff7905 /src/mainboard/razer/blade_stealth_kbl | |
| parent | bbfb18c41051caf26df5b6d56d1249bc1c90f0c3 (diff) | |
| download | coreboot-ab11f462191263e56ac539d532a365699d88b8f3.tar.gz coreboot-ab11f462191263e56ac539d532a365699d88b8f3.tar.bz2 coreboot-ab11f462191263e56ac539d532a365699d88b8f3.zip | |
mb/razer/blade_stealth_kbl: Disable UART #0 in devicetree
FSP-S disables UART #0 as per the `SerialIoDevMode` settings.
Change-Id: Ic1f9f7ce6fd4f453200d563bd8556946eef1b287
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Mimoja <coreboot@mimoja.de>
Diffstat (limited to 'src/mainboard/razer/blade_stealth_kbl')
| -rw-r--r-- | src/mainboard/razer/blade_stealth_kbl/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 655a0891899c..42ee0c7971e5 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -214,7 +214,7 @@ chip soc/intel/skylake device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 - device pci 1e.0 on end # Serial IO UART0 + device pci 1e.0 off end # Serial IO UART0 device pci 1e.6 off end # SDXC device pci 1f.0 on # LPC chip drivers/pc80/tpm |