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author | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-12 14:18:18 +0200 |
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committer | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-14 08:15:49 +0000 |
commit | 9ed0df4c380dc56a81a59a104b1ccac19cd52c35 (patch) | |
tree | ce96a0374015a55cf9a44e3fc490c1e70c39b236 /src/mainboard/roda/rk9/devicetree.cb | |
parent | d3a1a4171ee9f64f7721660f185b649ef874cc15 (diff) | |
download | coreboot-9ed0df4c380dc56a81a59a104b1ccac19cd52c35.tar.gz coreboot-9ed0df4c380dc56a81a59a104b1ccac19cd52c35.tar.bz2 coreboot-9ed0df4c380dc56a81a59a104b1ccac19cd52c35.zip |
sb/intel/i82801ix: Add common code to set up LPC IO decode ranges
This does the following:
- Add gen[1-4]_dec options to the devicetree to set up generic LPC
decode ranges in the southbridge code.
- Move setting up some default decode ranges to a common place. If
somehow a board needs to override this behavior it can happen in the
mb_setup_superio() hook (that will be renamed when moving to
C_ENVIRONMENT_BOOTBLOCK).
Change-Id: I3d904b1125bc410c11aa73a89b1969284e88dac1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/roda/rk9/devicetree.cb')
-rw-r--r-- | src/mainboard/roda/rk9/devicetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/roda/rk9/devicetree.cb b/src/mainboard/roda/rk9/devicetree.cb index 43001712076d..ddb2ad72a9d3 100644 --- a/src/mainboard/roda/rk9/devicetree.cb +++ b/src/mainboard/roda/rk9/devicetree.cb @@ -67,6 +67,8 @@ chip northbridge/intel/gm45 # Maybe we should set less for Mini PCIe. register "pcie_power_limits" = "{ { 10, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 }, { 10, 0 }, { 0, 0 } }" + register "gen1_dec" = "0x000c0601" + device pci 19.0 off end # LAN device pci 1a.0 on # UHCI ioapic_irq 2 INTA 0x10 |