nb/intel/gm45: Add C_ENVIRONMENT_BOOTBLOCK support

The i82801ix_early_init is now called both in the bootblock and
romstage. The rationale behind setting this up twice is to ensure
bootblock-romstage compatibility in the future if for instance VBOOT
is used.

This moves the console init to the bootblock.

The romstage now runs uncached. Adding a prog_run hooks to set up an
MTRR to cache the romstage will be done in a followup patch.

The default size of 64KiB is not modified for the bootblock as trying
to fit both EHCI and SPI flash debugging needs a more space and 64KiB
is the next power of 2 size that fits it.

TESTED on Thinkpad X200.

Change-Id: I8f59736cb54377973215f35e35d2cbcd1d82c374
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

3 files changed, 65 insertions, 46 deletions

diff --git a/src/mainboard/roda/rk9/Makefile.inc b/src/mainboard/roda/rk9/Makefile.inc
index 7ff15887cab2..1140e11d0f09 100644
--- a/src/mainboard/roda/rk9/Makefile.inc
+++ b/src/mainboard/roda/rk9/Makefile.inc
@@ -13,6 +13,8 @@
 ## GNU General Public License for more details.
 ##
 
+bootblock-y += bootblock.c
+
 romstage-y = gpio.c
 
 ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += ti_pci7xx1.c
diff --git a/src/mainboard/roda/rk9/bootblock.c b/src/mainboard/roda/rk9/bootblock.c
new file mode 100644
index 000000000000..454c3a04185e
--- /dev/null
+++ b/src/mainboard/roda/rk9/bootblock.c
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <arch/io.h>
+#include <device/pnp_ops.h>
+#include <superio/smsc/lpc47n227/lpc47n227.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, LPC47N227_SP1)
+
+void bootblock_mainboard_early_init(void)
+{
+	/* Original settings:
+	   idx 30 31 32 33 34 35 36 37  38 39
+	   val 60 00 00 40 00 ff 00 e0  00 80
+	   def 00 00 00 00 00 00 00 00  00 80
+
+	   Values:
+	   GP1 GP2 GP3 GP4
+	    fd  17  88  14
+	*/
+	const pnp_devfn_t sio = PNP_DEV(0x2e, 0);
+
+	/* Enter super-io's configuration state. */
+	pnp_enter_conf_state(sio);
+
+	/* Set lpc47n227's runtime register block's base address. */
+	pnp_write_config(sio, 0x30, 0x600 >> 4);
+
+	/* Set GP23 to alternate function. */
+	pnp_write_config(sio, 0x33, 0x40);
+
+	/* Set GP30 - GP37 to output mode: COM control */
+	pnp_write_config(sio, 0x35, 0xff);
+
+	/* Set GP45 - GP47 to output mode. */
+	pnp_write_config(sio, 0x37, 0xe0);
+
+	/* Set nIO_PME to open drain. */
+	pnp_write_config(sio, 0x39, 0x80);
+
+	/* Exit configuration state. */
+	pnp_exit_conf_state(sio);
+
+	/* Set GPIO output values: */
+	outb(0x88, 0x600 + 0xb + 3); /* GP30 - GP37 */
+	outb(0x10, 0x600 + 0xb + 4); /* GP40 - GP47 */
+
+	lpc47n227_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c
index b37b5c5f635e..48ca6b6b7df2 100644
--- a/src/mainboard/roda/rk9/romstage.c
+++ b/src/mainboard/roda/rk9/romstage.c
@@ -14,53 +14,7 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
-#include <device/pnp_ops.h>
 #include <northbridge/intel/gm45/gm45.h>
-#include <superio/smsc/lpc47n227/lpc47n227.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, LPC47N227_SP1)
-
-void mb_setup_superio(void)
-{
-	/* Original settings:
-	   idx 30 31 32 33 34 35 36 37  38 39
-	   val 60 00 00 40 00 ff 00 e0  00 80
-	   def 00 00 00 00 00 00 00 00  00 80
-
-	   Values:
-	   GP1 GP2 GP3 GP4
-	    fd  17  88  14
-	*/
-	const pnp_devfn_t sio = PNP_DEV(0x2e, 0);
-
-	/* Enter super-io's configuration state. */
-	pnp_enter_conf_state(sio);
-
-	/* Set lpc47n227's runtime register block's base address. */
-	pnp_write_config(sio, 0x30, 0x600 >> 4);
-
-	/* Set GP23 to alternate function. */
-	pnp_write_config(sio, 0x33, 0x40);
-
-	/* Set GP30 - GP37 to output mode: COM control */
-	pnp_write_config(sio, 0x35, 0xff);
-
-	/* Set GP45 - GP47 to output mode. */
-	pnp_write_config(sio, 0x37, 0xe0);
-
-	/* Set nIO_PME to open drain. */
-	pnp_write_config(sio, 0x39, 0x80);
-
-	/* Exit configuration state. */
-	pnp_exit_conf_state(sio);
-
-	/* Set GPIO output values: */
-	outb(0x88, 0x600 + 0xb + 3); /* GP30 - GP37 */
-	outb(0x10, 0x600 + 0xb + 4); /* GP40 - GP47 */
-
-	lpc47n227_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-}
 
 void get_mb_spd_addrmap(u8 *spd_addrmap)
 {