diff options
| author | Jan Samek <jan.samek@siemens.com> | 2022-10-04 14:47:00 +0200 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2022-10-27 08:41:16 +0000 |
| commit | 1ed09082827c9fa12ed81dca02abb2b8d022577f (patch) | |
| tree | 33d3b477756fdea23436c0370e5b601eaaef1e63 /src/mainboard/siemens/mc_apl1 | |
| parent | 40d3409dab132eb292eb4d46064168731c575734 (diff) | |
| download | coreboot-1ed09082827c9fa12ed81dca02abb2b8d022577f.tar.gz coreboot-1ed09082827c9fa12ed81dca02abb2b8d022577f.tar.bz2 coreboot-1ed09082827c9fa12ed81dca02abb2b8d022577f.zip | |
mb/siemens/mc_apl2: Enable early POST through NC_FPGA
Enable early POST code output for this mainboard, using
the NC FPGA device on PCIe.
This requires the parent PCI bridge to be initialized early.
BUG=none
TEST=boot on siemens/mc_apl2 and observe whether the POST
codes coming from before FSP-M init are visible
Change-Id: Ice5fe26e11d0513e6bb0a20f1d8f0483d7b3dc6a
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/mainboard/siemens/mc_apl1')
3 files changed, 28 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig index 933e594fb5b2..99ebc6e2578a 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS select DRIVERS_I2C_RX6110SA select RX6110SA_DISABLE_ACPI select DRIVER_SIEMENS_NC_FPGA + select NC_FPGA_POST_CODE select MAINBOARD_HAS_TPM2 select MEMORY_MAPPED_TPM select TPM_ON_FAST_SPI @@ -27,4 +28,19 @@ config VBOOT config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/mc_apl_vboot.fmd" +config EARLY_PCI_BRIDGE_DEVICE + hex + depends on NC_FPGA_POST_CODE + default 0x13 + +config EARLY_PCI_BRIDGE_FUNCTION + hex + depends on NC_FPGA_POST_CODE + default 0x1 + +config EARLY_PCI_MMIO_BASE + hex + depends on NC_FPGA_POST_CODE + default 0xfe800000 + endif # BOARD_SIEMENS_MC_APL2 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc index 152b46ece113..9ec2c8024f2e 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc @@ -2,3 +2,5 @@ bootblock-y += gpio.c ramstage-y += gpio.c ramstage-y += mainboard.c + +all-$(CONFIG_NC_FPGA_POST_CODE) += post.c diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/post.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/post.c new file mode 100644 index 000000000000..c34e2539bc2f --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/post.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <nc_fpga.h> +#include <types.h> + +void mainboard_post(uint8_t value) +{ + nc_fpga_post(value); +} |