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| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2023-05-22 14:45:42 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-06-01 15:41:46 +0000 |
| commit | 6256fb63fff9db1e7f77f58da5c9514eb783c199 (patch) | |
| tree | b7926a4f6f048bc227fe3e76eb3db658e841a2ad /src/mainboard/siemens/mc_apl1 | |
| parent | f165bbdcf043dd9753c3b3a8e4ae86b0bfcd78ee (diff) | |
| download | coreboot-6256fb63fff9db1e7f77f58da5c9514eb783c199.tar.gz coreboot-6256fb63fff9db1e7f77f58da5c9514eb783c199.tar.bz2 coreboot-6256fb63fff9db1e7f77f58da5c9514eb783c199.zip | |
mb/siemens/{mc_apl2,mc_apl5,mc_apl6}: Limit SATA speed to Gen 2
Due to mainboard restrictions a SATA link at Gen 3 can cause issues as
the margin is not big enough. Limit SATA speed to Gen 2 to achieve a
more robust SATA connection.
Change-Id: Ifdea4542836b9c75b5507324fbb06b9566a6fe1d
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75365
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/siemens/mc_apl1')
3 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index b515170ad03c..2b2c32d083ab 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -70,6 +70,7 @@ chip soc/intel/apollolake register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "DisableSataSalpSupport" = "1" + register "sata_speed" = "SATA_GEN2" end device pci 13.0 on # - RP 2 - PCIe A 0 register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb index 92bba650478c..15ca3f117d80 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb @@ -70,6 +70,7 @@ chip soc/intel/apollolake register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "DisableSataSalpSupport" = "1" + register "sata_speed" = "SATA_GEN2" end device pci 13.0 on # - RP 2 - PCIe A 0 register "pcie_rp_clkreq_pin[2]" = "0" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb index 8223f68babca..3c907e3c7814 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb @@ -41,6 +41,7 @@ chip soc/intel/apollolake register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "DisableSataSalpSupport" = "1" + register "sata_speed" = "SATA_GEN2" end device pci 13.0 on # - RP 2 - PCIe A 0 register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" |