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| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2023-05-31 14:36:22 +0200 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2023-06-02 17:58:46 +0000 |
| commit | 7e5b28feb6a0b14c4303b9610bee3277dd8077fe (patch) | |
| tree | 9045f9d524e05113c8b58b2264651651e40bf2b0 /src/mainboard/siemens/mc_apl1 | |
| parent | 923215184d3720d836c2be75a95c629af6dac7c9 (diff) | |
| download | coreboot-7e5b28feb6a0b14c4303b9610bee3277dd8077fe.tar.gz coreboot-7e5b28feb6a0b14c4303b9610bee3277dd8077fe.tar.bz2 coreboot-7e5b28feb6a0b14c4303b9610bee3277dd8077fe.zip | |
soc/intel/apollolake: Switch to snake case for SataPortsEnable
For a unification of the naming convension, change from pascal case to
snake case style for parameter 'SataPortsEnable'.
Change-Id: I0df35125360eb42a03d5445011d72842cb2b8d7e
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75553
Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Diffstat (limited to 'src/mainboard/siemens/mc_apl1')
6 files changed, 12 insertions, 12 deletions
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb index a08f053d8c58..5d4acd85ab83 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb @@ -69,8 +69,8 @@ chip soc/intel/apollolake device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on # - SATA - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" + register "sata_ports_enable[0]" = "1" + register "sata_ports_enable[1]" = "1" register "DisableSataSalpSupport" = "1" end device pci 13.0 on # - RP 2 - PCIe A 0 - MACPHY diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index 129149711f12..705441330547 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -67,8 +67,8 @@ chip soc/intel/apollolake device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on # - SATA - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" + register "sata_ports_enable[0]" = "1" + register "sata_ports_enable[1]" = "1" register "sata_ports_ssd[0]" = "1" register "sata_ports_ssd[1]" = "1" register "DisableSataSalpSupport" = "1" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb index 56d93aa30ded..472f5baddc04 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb @@ -64,8 +64,8 @@ chip soc/intel/apollolake device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on # - SATA - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" + register "sata_ports_enable[0]" = "1" + register "sata_ports_enable[1]" = "1" register "DisableSataSalpSupport" = "1" end device pci 13.0 on # - RP 2 - PCIe A 0 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb index 1c5f7970ef09..baaff1e96095 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb @@ -58,8 +58,8 @@ chip soc/intel/apollolake device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on # - SATA - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" + register "sata_ports_enable[0]" = "1" + register "sata_ports_enable[1]" = "1" register "DisableSataSalpSupport" = "1" end device pci 13.0 on # - RP 2 - PCIe A 0 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb index b308ab2519df..52fcd49df69b 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb @@ -67,8 +67,8 @@ chip soc/intel/apollolake device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on # - SATA - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" + register "sata_ports_enable[0]" = "1" + register "sata_ports_enable[1]" = "1" register "sata_ports_ssd[0]" = "1" register "sata_ports_ssd[1]" = "1" register "DisableSataSalpSupport" = "1" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb index 1885e817f0a0..dc66be63bda3 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb @@ -38,8 +38,8 @@ chip soc/intel/apollolake device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on # - SATA - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" + register "sata_ports_enable[0]" = "1" + register "sata_ports_enable[1]" = "1" register "sata_ports_ssd[0]" = "1" register "sata_ports_ssd[1]" = "1" register "DisableSataSalpSupport" = "1" |