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| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2022-11-10 09:46:17 +0100 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-11-24 06:01:58 +0000 |
| commit | e19f40377078375ed85f27e5028ed17d7857d6ca (patch) | |
| tree | 076e547950025dd4af6cec4b07f954008c70e723 /src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb | |
| parent | 155cf5cd2ee844e9fb86f0f2487ccca65e560f33 (diff) | |
| download | coreboot-e19f40377078375ed85f27e5028ed17d7857d6ca.tar.gz coreboot-e19f40377078375ed85f27e5028ed17d7857d6ca.tar.bz2 coreboot-e19f40377078375ed85f27e5028ed17d7857d6ca.zip | |
mb/siemens/mc_ehl2: Enable Marvell PHY interrupt
On this mainboard Marvell PHY INTn is routed to LED[2] pin.
Change-Id: I28a78afdcf0599bb998f906ce8056a0586e24f33
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69434
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb')
| -rw-r--r-- | src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index b8ea1b6213e7..8090927661c4 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -189,6 +189,8 @@ chip soc/intel/elkhartlake register "led_0_ctrl" = "7" # LED[1]: On - Link, Blink - Activity, Off - No Link register "led_1_ctrl" = "1" + # INTn is routed to LED[2] pin + register "enable_int" = "true" device mdio 0 on # PHY address ops m88e1512_ops end @@ -202,6 +204,8 @@ chip soc/intel/elkhartlake register "led_0_ctrl" = "7" # LED[1]: On - Link, Blink - Activity, Off - No Link register "led_1_ctrl" = "1" + # INTn is routed to LED[2] pin + register "enable_int" = "true" device mdio 1 on # PHY address ops m88e1512_ops end @@ -218,6 +222,8 @@ chip soc/intel/elkhartlake register "led_0_ctrl" = "7" # LED[1]: On - Link, Blink - Activity, Off - No Link register "led_1_ctrl" = "1" + # INTn is routed to LED[2] pin + register "enable_int" = "true" device mdio 1 on # PHY address ops m88e1512_ops end |