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| author | Werner Zeh <werner.zeh@siemens.com> | 2022-12-22 12:58:14 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-01-11 21:05:44 +0000 |
| commit | 2f46a1780b5bdd60292dce0049a88d71eb873be6 (patch) | |
| tree | 62d639bc28aba49b820e3e5b0e86cf9348d6aa2f /src/mainboard/siemens/mc_ehl | |
| parent | adbdc5c1bdca62b567c8347e6189427304ee6409 (diff) | |
| download | coreboot-2f46a1780b5bdd60292dce0049a88d71eb873be6.tar.gz coreboot-2f46a1780b5bdd60292dce0049a88d71eb873be6.tar.bz2 coreboot-2f46a1780b5bdd60292dce0049a88d71eb873be6.zip | |
mb/siemens/mc_ehl1: Enable real-time tuning
Enable the real-time tuning to improve performance in the real-time
environment for this mainboard.
Change-Id: I91ad7ca58add92b5cc66148aff8378890ee217eb
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71234
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/siemens/mc_ehl')
| -rw-r--r-- | src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index 82070785fcfc..e67004eff654 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -136,6 +136,9 @@ chip soc/intel/elkhartlake # Disable L1 prefetcher register "L1_prefetcher_disable" = "true" + # Enable real-time tuning + register "realtime_tuning_enable" = "true" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device |