diff options
| author | Philipp Hug <philipp@hug.cx> | 2018-09-13 22:16:36 +0200 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2018-09-14 09:51:02 +0000 |
| commit | 374d992fc831300377216fd3f7c3137d4b53ab36 (patch) | |
| tree | 73f0c880bb41c08b861f0e8796f7cf3223616b73 /src/mainboard/sifive | |
| parent | c014ef59191c512100a0596f998ffb9926fc8eb0 (diff) | |
| download | coreboot-374d992fc831300377216fd3f7c3137d4b53ab36.tar.gz coreboot-374d992fc831300377216fd3f7c3137d4b53ab36.tar.bz2 coreboot-374d992fc831300377216fd3f7c3137d4b53ab36.zip | |
soc/sifive/fu540: Switch clock to 1GHz in romstage
Invoke clock_init in romstage for SiFive Unleashed.
Change-Id: Ib869762d557e8fdf4c83a53698102df116d80389
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/sifive')
| -rw-r--r-- | src/mainboard/sifive/hifive-unleashed/romstage.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/mainboard/sifive/hifive-unleashed/romstage.c b/src/mainboard/sifive/hifive-unleashed/romstage.c index ea6efb9b6d25..9729f86f4af1 100644 --- a/src/mainboard/sifive/hifive-unleashed/romstage.c +++ b/src/mainboard/sifive/hifive-unleashed/romstage.c @@ -13,8 +13,13 @@ * GNU General Public License for more details. */ +#include <cbmem.h> #include <console/console.h> +#include <console/streams.h> +#include <console/uart.h> #include <program_loading.h> +#include <soc/clock.h> +#include <soc/sdram.h> void main(void) { @@ -22,5 +27,18 @@ void main(void) /* TODO: Follow Section 6.3 (FSBL) of the FU540 manual */ + /* + * Flush console before changing clock/UART divisor to prevent garbage + * being printed. + */ + console_tx_flush(); + + clock_init(); + + // re-initialize UART + #if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + uart_init(CONFIG_UART_FOR_CONSOLE); + #endif + run_ramstage(); } |