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authorSean Rhodes <sean@starlabs.systems>2023-02-02 15:53:03 +0000
committerFelix Held <felix-coreboot@felixheld.de>2023-03-10 13:51:01 +0000
commitfe2f50f49669dead4e39a16a50fac9d5f1465078 (patch)
treeee52a6c8fb0d21f6fc62c01b719841291f502d9f /src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
parentab4ace2b8c807fd956e6ae21e8922cb4ca69ab5e (diff)
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mb/starlabs/starbook/adl: Enable ASPM
Enable ASPM for RP5 (wireless) and RP9 (SSD). Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I428040caf171bdcfedc285cdeddc55bcbec40f3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72753 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/starlabs/starbook/variants/adl/devicetree.cb')
-rw-r--r--src/mainboard/starlabs/starbook/variants/adl/devicetree.cb5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
index 4b833ffa60f3..c43f6a6ebab1 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
@@ -100,6 +100,8 @@ chip soc/intel/alderlake
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
+ .PcieRpL1Substates = L1_SS_L1_2,
+ .pcie_rp_aspm = ASPM_L0S_L1,
}"
smbios_slot_desc "SlotTypePciExpressGen3X1"
"SlotLengthShort"
@@ -117,6 +119,9 @@ chip soc/intel/alderlake
.clk_src = 1,
.clk_req = 1,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
+ .PcieRpL1Substates = L1_SS_L1_2,
+ .pcie_rp_aspm = ASPM_L0S_L1,
+
}"
smbios_slot_desc "SlotTypeM2Socket3"
"SlotLengthLong"