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| author | Sean Rhodes <sean@starlabs.systems> | 2022-07-03 22:38:24 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-07-05 13:06:32 +0000 |
| commit | fa7970aa81543cab7b508954a93a99e9bb6b6493 (patch) | |
| tree | 788e5d98d35e01d52a0f3c5501d4793722e57b38 /src/mainboard/starlabs | |
| parent | 2eb2dcebc7b09a315b4f7c6bdc8f4abf4220de61 (diff) | |
| download | coreboot-fa7970aa81543cab7b508954a93a99e9bb6b6493.tar.gz coreboot-fa7970aa81543cab7b508954a93a99e9bb6b6493.tar.bz2 coreboot-fa7970aa81543cab7b508954a93a99e9bb6b6493.zip | |
mb/starlabs/labtop/tgl: Nit - minor format change
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I068c6e46d85d869afc72280509a03d5ff682b917
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65618
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/starlabs')
| -rw-r--r-- | src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb index cab707dea4fb..c5f7040058f4 100644 --- a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb @@ -6,12 +6,12 @@ chip soc/intel/tigerlake # Graphics # Not used but timings left for reference # register "panel_cfg" = "{ - # .up_delay_ms = 2000, // T3 - # .backlight_on_delay_ms = 0, // T7 - # .backlight_off_delay_ms = 2000, // T9 - # .down_delay_ms = 500, // T10 - # .cycle_delay_ms = 500, // T12 - # .backlight_pwm_hz = 200, // PWM + # .up_delay_ms = 2000, // T3 + # .backlight_on_delay_ms = 0, // T7 + # .backlight_off_delay_ms = 2000, // T9 + # .down_delay_ms = 500, // T10 + # .cycle_delay_ms = 500, // T12 + # .backlight_pwm_hz = 200, // PWM # }" # FSP Memory @@ -195,7 +195,7 @@ chip soc/intel/tigerlake chip drivers/pc80/tpm device pnp 0c31.0 on end - end + end chip ec/starlabs/merlin # Port pair 4Eh/4Fh |