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| author | Angel Pons <th3fanbus@gmail.com> | 2021-06-04 11:18:39 +0200 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-06-07 04:53:39 +0000 |
| commit | 0caf80d8aaa383d40618343f14ed78774108053d (patch) | |
| tree | 58dcb504e8ac9e4d6d6aff1ea7749b89c7fc432b /src/mainboard/supermicro/x9scl/devicetree.cb | |
| parent | d4e68eb4147c5306f50e027950142db9ba46609c (diff) | |
| download | coreboot-0caf80d8aaa383d40618343f14ed78774108053d.tar.gz coreboot-0caf80d8aaa383d40618343f14ed78774108053d.tar.bz2 coreboot-0caf80d8aaa383d40618343f14ed78774108053d.zip | |
bd82x6x boards: Drop redundant `c2_latency`
If unspecified, chipset code already uses 101, and 0x65 == 101.
Change-Id: I524ca492fa577003df23017756f74a455582132f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/mainboard/supermicro/x9scl/devicetree.cb')
| -rw-r--r-- | src/mainboard/supermicro/x9scl/devicetree.cb | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/supermicro/x9scl/devicetree.cb b/src/mainboard/supermicro/x9scl/devicetree.cb index 13b20437ab9a..49fcff5a6df9 100644 --- a/src/mainboard/supermicro/x9scl/devicetree.cb +++ b/src/mainboard/supermicro/x9scl/devicetree.cb @@ -16,7 +16,6 @@ chip northbridge/intel/sandybridge device pci 02.0 off end # iGPU device pci 06.0 on end # PEG chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" register "gen1_dec" = "0x00fc0a01" # NCT6776 SuperIO (0x0a00-0aff) register "gen2_dec" = "0x00fc1641" # WPCM450 SuperIO (0x1600-16ff) register "gen3_dec" = "0x00040ca1" # IPMI KCS (0x0ca0-0ca3) |