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author | Tim Crawford <tcrawford@system76.com> | 2022-07-17 16:21:52 -0600 |
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committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | 2022-07-23 20:03:25 +0000 |
commit | 0d27fb8c44eab9af22001b342b807cd761469750 (patch) | |
tree | b173b895f557d3c6178d4a02aee6bf4e9e06c461 /src/mainboard/system76/tgl-u/acpi/sleep.asl | |
parent | ff93c93fefbe19e0f149c70eac816a69ec011ac6 (diff) | |
download | coreboot-0d27fb8c44eab9af22001b342b807cd761469750.tar.gz coreboot-0d27fb8c44eab9af22001b342b807cd761469750.tar.bz2 coreboot-0d27fb8c44eab9af22001b342b807cd761469750.zip |
mb/system76/tgl-u: Convert lemp10 to variant setup
Change-Id: I11f2ebb94b0e9a3e2c18c5b2071ccc3e03c16655
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/system76/tgl-u/acpi/sleep.asl')
-rw-r--r-- | src/mainboard/system76/tgl-u/acpi/sleep.asl | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/src/mainboard/system76/tgl-u/acpi/sleep.asl b/src/mainboard/system76/tgl-u/acpi/sleep.asl new file mode 100644 index 000000000000..83888f3e59e9 --- /dev/null +++ b/src/mainboard/system76/tgl-u/acpi/sleep.asl @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/gpio.h> + +Method (PGPM, 1, Serialized) +{ + For (Local0 = 0, Local0 < 6, Local0++) + { + \_SB.PCI0.CGPM (Local0, Arg0) + } +} + +/* + * Method called from _PTS prior to system sleep state entry + * Enables dynamic clock gating for all 5 GPIO communities + */ +Method (MPTS, 1, Serialized) +{ + \_SB.PCI0.LPCB.EC0.PTS (Arg0) + PGPM (MISCCFG_GPIO_PM_CONFIG_BITS) +} + +/* + * Method called from _WAK prior to system sleep state wakeup + * Disables dynamic clock gating for all 5 GPIO communities + */ +Method (MWAK, 1, Serialized) +{ + PGPM (0) + \_SB.PCI0.LPCB.EC0.WAK (Arg0) +} + +/* + * S0ix Entry/Exit Notifications + * Called from \_SB.PEPD._DSM + */ +Method (MS0X, 1, Serialized) +{ + If (Arg0 == 1) { + /* S0ix Entry */ + PGPM (MISCCFG_GPIO_PM_CONFIG_BITS) + } Else { + /* S0ix Exit */ + PGPM (0) + } +} |