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authorJason Glenesk <jason.glenesk@amd.corp-partner.google.com>2021-03-10 03:50:57 -0800
committerPatrick Georgi <pgeorgi@google.com>2021-04-16 06:50:14 +0000
commit79542fa36f919647137737ce2cf2e30042e4fe53 (patch)
treea8503f15568da9d506a6517cbe30adf7ca7e9b81 /src/mainboard/system76/whl-u/variants/darp5/overridetree.cb
parent40df8aa84bcdb13b5b7213d90eca04c3f4f6c6ac (diff)
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soc/amd/cezanne: Port ACPI p-state and c-state entries from picasso
Add generate_cpu_entries to device operations. Add support to generate cpu p-state and c-state SSDT entries. BUG=b:184151560 TEST=Dump and verify SSDT entry for CPU p-states and c-states. Change-Id: I77d8078b94fb661dc045b4184955c8cbec373d12 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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