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| author | Tim Crawford <tcrawford@system76.com> | 2023-01-04 10:01:05 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-01-13 16:42:14 +0000 |
| commit | d7c8d7d7c5cf76c86073f7455f1467fd5c2e41ff (patch) | |
| tree | 6739f8cacd84384f0492e2e3c1a5c8df275679da /src/mainboard/system76 | |
| parent | e51f96f7414e3b7a19175976ee675373663e96e3 (diff) | |
| download | coreboot-d7c8d7d7c5cf76c86073f7455f1467fd5c2e41ff.tar.gz coreboot-d7c8d7d7c5cf76c86073f7455f1467fd5c2e41ff.tar.bz2 coreboot-d7c8d7d7c5cf76c86073f7455f1467fd5c2e41ff.zip | |
mb/system76/adl-p: Enable AER on CPU PCIe RP
Tested with the following drives:
- Crucial P5 Plus (CT500P5PSSD8)
- Kingston KC3000 (SKC3000S/512G)
- Sabrent Rocket NVMe 4.0 (SB-ROCKET-NVMEe4-500)
- Samsung 970 EVO (MZ-V7E250)
- Samsung 970 EVO Plus (MZ-V7S250)
- Samsung 980 PRO (MZ-V8P2T0)
- WD Black SN850X (WDS100T2XD0E)
- WD Blue SN580 (WDS500G2B0C)
- WD Green SN350 (WDS240G2G0C)
Test:
- Drive is functional and has no unrecoverable errors on boot
- Drive is functional and has no unrecoverable errors after S0ix
Change-Id: I51492c97c48f760d4aa9e4a2b2e57b0f1a06d090
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Diffstat (limited to 'src/mainboard/system76')
| -rw-r--r-- | src/mainboard/system76/adl-p/variants/darp8/overridetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/system76/adl-p/variants/galp6/overridetree.cb | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/system76/adl-p/variants/darp8/overridetree.cb b/src/mainboard/system76/adl-p/variants/darp8/overridetree.cb index 4caed3a1733a..5f82c443c016 100644 --- a/src/mainboard/system76/adl-p/variants/darp8/overridetree.cb +++ b/src/mainboard/system76/adl-p/variants/darp8/overridetree.cb @@ -20,7 +20,7 @@ chip soc/intel/alderlake register "cpu_pcie_rp[CPU_RP(1)]" = "{ .clk_src = 0, .clk_req = 0, - .flags = PCIE_RP_LTR, + .flags = PCIE_RP_LTR | PCIE_RP_AER, }" chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD2_PWR_EN diff --git a/src/mainboard/system76/adl-p/variants/galp6/overridetree.cb b/src/mainboard/system76/adl-p/variants/galp6/overridetree.cb index e63e185c1fea..c10e17adbc9d 100644 --- a/src/mainboard/system76/adl-p/variants/galp6/overridetree.cb +++ b/src/mainboard/system76/adl-p/variants/galp6/overridetree.cb @@ -18,7 +18,7 @@ chip soc/intel/alderlake register "cpu_pcie_rp[CPU_RP(1)]" = "{ .clk_src = 0, .clk_req = 0, - .flags = PCIE_RP_LTR, + .flags = PCIE_RP_LTR | PCIE_RP_AER, }" chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD1_PWR_EN |