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| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2019-04-24 14:21:04 +0800 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2019-04-24 15:51:22 +0000 |
| commit | 18060d7d92a924dde1aff73f7792e64c6c0c34cd (patch) | |
| tree | aa08b62b6951d556f5695aa56266d364db5aad4c /src/mainboard | |
| parent | d228c1ef32daf0affe211cd8e79b31e0a2e5f45c (diff) | |
| download | coreboot-18060d7d92a924dde1aff73f7792e64c6c0c34cd.tar.gz coreboot-18060d7d92a924dde1aff73f7792e64c6c0c34cd.tar.bz2 coreboot-18060d7d92a924dde1aff73f7792e64c6c0c34cd.zip | |
mb/google/sarien: Disable touch by strap pin GPP_B4
We want to disable touch for non-touch sku. We can use
strap pin GPP_B4 to identify it is connected with touch
or not.
touch sku: GPP_B4 is low
non-touch sku: GPP_B4 is high
BUG=b:131132419
TEST=boot up and check no touch device exist
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If6681262c25e4b01e061a8520e38905d40345509
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32438
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/sarien/variants/sarien/devicetree.cb | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 625655b38c27..12e5dea4aac8 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -329,6 +329,8 @@ chip soc/intel/cannonlake register "generic.enable_off_delay_ms" = "100" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" + register "generic.device_present_gpio" = "GPP_B4" + register "generic.device_present_gpio_invert" = "1" device i2c 10 on end end chip drivers/i2c/generic @@ -339,6 +341,8 @@ chip soc/intel/cannonlake register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" register "enable_delay_ms" = "5" register "has_power_resource" = "1" + register "device_present_gpio" = "GPP_B4" + register "device_present_gpio_invert" = "1" device i2c 34 on end end end # I2C #0 |