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authorKapil Porwal <kapilporwal@google.com>2023-01-16 16:07:48 +0000
committerFelix Held <felix-coreboot@felixheld.de>2023-02-23 12:15:35 +0000
commit23ef60de984bb67e90cc08edb2852d989d47c616 (patch)
treeb145429a19680424848405c54c9f79fc8e19f217 /src/mainboard
parentc071652a4e6ad8deb319663f400fd46cf9114947 (diff)
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intel/alderlake: remove skip_mbp_hob SOC chip config
Introduce at new config option CONFIG_FSP_PUBLISH_MBP_HOB to control the creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. This new option is hooked with `SkipMbpHob` UPD and is always disabled for RPL & ADL-N based ChromeOS platforms. It is not disabled for ADL-P based platforms because ADL-P FSP relies on MBP HOB for ChipsetInit version for ChipsetInit sync. As ChipsetInit sync doesn't occur if no MBP HOB, so it results S0ix issue. This limitation is addressed in the later platforms so creation of MBP HOB can be skipped for ADL-N and RPL based platforms. This made skip_mbp_hob SOC chip config variable redundant which is also removed as part of this change. BUG=none TEST=Build and boot to Google/Taniks. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ia396b633a71aedf592c45b69063ee0528840fd2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb2
-rw-r--r--src/mainboard/google/brya/variants/marasov/overridetree.cb2
-rw-r--r--src/mainboard/intel/adlrvp/devicetree_n.cb2
3 files changed, 0 insertions, 6 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
index 16c7ce02df26..ad5b1f8dbc1f 100644
--- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
@@ -89,8 +89,6 @@ chip soc/intel/alderlake
# Disable Package C-state demotion for nissa baseboard.
register "disable_package_c_state_demotion" = "1"
- register "skip_mbp_hob" = "1"
-
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
diff --git a/src/mainboard/google/brya/variants/marasov/overridetree.cb b/src/mainboard/google/brya/variants/marasov/overridetree.cb
index e09166df6921..4cc87907d64d 100644
--- a/src/mainboard/google/brya/variants/marasov/overridetree.cb
+++ b/src/mainboard/google/brya/variants/marasov/overridetree.cb
@@ -66,8 +66,6 @@ chip soc/intel/alderlake
}"
register "sagv" = "SaGv_Enabled"
- register "skip_mbp_hob" = "1"
-
register "ext_fivr_settings" = "{
.configure_ext_fivr = 1,
.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX,
diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb
index b54a13453054..6776284fe061 100644
--- a/src/mainboard/intel/adlrvp/devicetree_n.cb
+++ b/src/mainboard/intel/adlrvp/devicetree_n.cb
@@ -150,8 +150,6 @@ chip soc/intel/alderlake
.vnn_icc_max_ma = 500,
}"
- register "skip_mbp_hob" = "1"
-
device domain 0 on
device ref igpu on end
device ref dtt on