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| author | Robert Chen <robert.chen@quanta.corp-partner.google.com> | 2023-02-23 04:13:04 -0500 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-02-24 16:34:32 +0000 |
| commit | 3053a021b62af324f11553fc9c50ed2d2b7eb7dc (patch) | |
| tree | a76b4f629f03ee878630685016c0174bf1ea6332 /src/mainboard | |
| parent | 1ebf341b17df2d83e87f3e8b51f206e6eba25b38 (diff) | |
| download | coreboot-3053a021b62af324f11553fc9c50ed2d2b7eb7dc.tar.gz coreboot-3053a021b62af324f11553fc9c50ed2d2b7eb7dc.tar.bz2 coreboot-3053a021b62af324f11553fc9c50ed2d2b7eb7dc.zip | |
Revert "mb/google/brya/var/lisbon: Update gpio table"
This reverts commit 0e0f9e51c4c4f190cbe7ef5bffa138601c644d3c.
Reason for revert:
PLTRST only keeps 18xms and it's too short for eMMC disk fully reset.
Change-Id: I13b93747bdb4d39de1ffcfdc020648871fa6e048
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73203
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/brya/variants/lisbon/gpio.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/mainboard/google/brya/variants/lisbon/gpio.c b/src/mainboard/google/brya/variants/lisbon/gpio.c index 443d59c6074a..1dfef5ceb0f9 100644 --- a/src/mainboard/google/brya/variants/lisbon/gpio.c +++ b/src/mainboard/google/brya/variants/lisbon/gpio.c @@ -25,7 +25,7 @@ static const struct pad_config override_gpio_table[] = { /* B2 : VRALERT# ==> M2_SSD_PLA_L */ PAD_NC(GPP_B2, NONE), /* B3 : PROC_GP2 ==> EMMC_PERST_L */ - PAD_CFG_GPO_LOCK(GPP_B3, 1, LOCK_CONFIG), + PAD_CFG_GPO(GPP_B3, 1, DEEP), /* B7 : ISH_12C1_SDA ==> PCH_I2C_MISCB_SDA */ PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), /* B8 : ISH_I2C1_SCL ==> PCH_I2C_MISCB_SCL */ @@ -91,6 +91,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), /* A21 : DDPC_CTRCLK ==> EN_PP3300_EMMC */ PAD_CFG_GPO(GPP_A21, 1, DEEP), + /* B3 : PROC_GP2 ==> EMMC_PERST_L */ + PAD_CFG_GPO(GPP_B3, 0, DEEP), /* B4 : PROC_GP3 ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_B4, 0, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ @@ -134,6 +136,8 @@ static const struct pad_config early_gpio_table[] = { }; static const struct pad_config romstage_gpio_table[] = { + /* B3 : PROC_GP2 ==> EMMC_PERST_L */ + PAD_CFG_GPO(GPP_B3, 1, DEEP), /* B4 : PROC_GP3 ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_B4, 1, DEEP), }; |