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| author | Michael Niewöhner <foss@mniewoehner.de> | 2019-09-22 21:56:17 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2021-04-22 22:44:57 +0000 |
| commit | 305b6488e4cd4adfc7427938928dca51f4d70dd7 (patch) | |
| tree | 73f6b0a2d96e14e577e0026590dcb5858f9c9ff8 /src/mainboard | |
| parent | 348f2a63707cc1711cc836837fc7f5b36b2e0553 (diff) | |
| download | coreboot-305b6488e4cd4adfc7427938928dca51f4d70dd7.tar.gz coreboot-305b6488e4cd4adfc7427938928dca51f4d70dd7.tar.bz2 coreboot-305b6488e4cd4adfc7427938928dca51f4d70dd7.zip | |
soc/intel/cannonlake: set MSR LT_LOCK_MEMORY at end of POST
FSP does not set the MSR LT_LOCK_MEMORY when SkipMpInit=1. Therefore,
set LT_LOCK_MEMORY at end of POST, when native MP init is used, to
protect SMM in accordance to Intel BWG.
Test on clevo/cml-u: chipsec says LT_LOCK_MEMORY is locked.
Change-Id: Iaadd4996653c4f27d268b1c4773c1e2e86114912
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36356
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
0 files changed, 0 insertions, 0 deletions