mb/google/guybrush: Update romstage power-on timings for PCIe

This configures the romstage portion of the PCIe GPIOs in the correct
sequence to meet the power-on timings.

The PCIe_RST line is anded with the Aux reset lines, so to take the PCIe
devices out of reset, both need to be brought hign.

BUG=b:184796302, b:184598323
TEST=Verify timings between GPIO init sections.  All available modules
are present after training.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ib1990bba31c84827467d4ff8a15f1e0682501e70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54741
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

7 files changed, 73 insertions, 0 deletions

diff --git a/src/mainboard/google/guybrush/Makefile.inc b/src/mainboard/google/guybrush/Makefile.inc
index d4eeaf5e5638..ecd031a85f3b 100644
--- a/src/mainboard/google/guybrush/Makefile.inc
+++ b/src/mainboard/google/guybrush/Makefile.inc
@@ -11,6 +11,7 @@ $(info APCB sources not found.  Skipping APCB.)
 endif
 
 romstage-y += port_descriptors.c
+romstage-y += romstage.c
 
 ramstage-y += mainboard.c
 ramstage-y += ec.c
diff --git a/src/mainboard/google/guybrush/romstage.c b/src/mainboard/google/guybrush/romstage.c
new file mode 100644
index 000000000000..23e7853a0511
--- /dev/null
+++ b/src/mainboard/google/guybrush/romstage.c
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <soc/platform_descriptors.h>
+
+void mb_pre_fspm(void)
+{
+	size_t base_num_gpios, override_num_gpios;
+	const struct soc_amd_gpio *base_gpios, *override_gpios;
+
+	/* Initialize PCIe reset. */
+	base_gpios = variant_pcie_gpio_table(&base_num_gpios);
+	override_gpios = variant_pcie_override_gpio_table(&override_num_gpios);
+
+	gpio_configure_pads_with_override(base_gpios, base_num_gpios,
+			override_gpios, override_num_gpios);
+
+}
diff --git a/src/mainboard/google/guybrush/variants/baseboard/Makefile.inc b/src/mainboard/google/guybrush/variants/baseboard/Makefile.inc
index e6a64a8dcae4..d8fce0a6ebc6 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/Makefile.inc
+++ b/src/mainboard/google/guybrush/variants/baseboard/Makefile.inc
@@ -3,6 +3,7 @@ bootblock-y += helpers.c
 
 romstage-y += helpers.c
 romstage-y += tpm_tis.c
+romstage-y += gpio.c
 
 ramstage-y += gpio.c
 ramstage-y += helpers.c
diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c
index dc72cdb5c67a..0b418d8b58e1 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c
+++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c
@@ -253,6 +253,29 @@ static const struct soc_amd_gpio sleep_gpio_table[] = {
 	/* TODO: Fill sleep gpio configuration */
 };
 
+/* PCIE_RST needs to be brought high before FSP-M runs */
+static const struct soc_amd_gpio pcie_gpio_table[] = {
+/* Disable all AUX_RESET lines & PCIE_RST */
+	/* WWAN_AUX_RESET_L */
+	PAD_GPO(GPIO_18, HIGH),
+	/* WLAN_AUX_RESET (ACTIVE HIGH) */
+	PAD_GPO(GPIO_29, LOW),
+	/* SSD_AUX_RESET_L */
+	PAD_GPO(GPIO_40, HIGH),
+	/* SD_AUX_RESET_L */
+	PAD_GPO(GPIO_69, HIGH),
+	/* BID>1: Unused TP27; BID==1: SD_AUX_RESET_L */
+	PAD_NC(GPIO_70),
+	/* PCIE_RST0_L */
+	PAD_NFO(GPIO_26, PCIE_RST_L, HIGH),
+};
+
+const struct soc_amd_gpio *__weak variant_pcie_gpio_table(size_t *size)
+{
+	*size = ARRAY_SIZE(pcie_gpio_table);
+	return pcie_gpio_table;
+}
+
 const struct soc_amd_gpio *__weak variant_bootblock_gpio_table(size_t *size)
 {
 	*size = ARRAY_SIZE(bootblock_gpio_table);
@@ -282,6 +305,12 @@ const struct soc_amd_gpio * __weak variant_bootblock_override_gpio_table(size_t
 	return NULL;
 }
 
+const struct soc_amd_gpio * __weak variant_pcie_override_gpio_table(size_t *size)
+{
+	*size = 0;
+	return NULL;
+}
+
 const struct soc_amd_gpio *__weak variant_early_gpio_table(size_t *size)
 {
 	*size = ARRAY_SIZE(early_gpio_table);
diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
index f1bbfd3b469e..243f7ff884d2 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
@@ -25,6 +25,7 @@ const struct soc_amd_gpio *variant_base_gpio_table(size_t *size);
 const struct soc_amd_gpio *variant_override_gpio_table(size_t *size);
 const struct soc_amd_gpio *variant_early_override_gpio_table(size_t *size);
 const struct soc_amd_gpio *variant_bootblock_override_gpio_table(size_t *size);
+const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size);
 
 /* This function provides early GPIO init in early bootblock or psp. */
 const struct soc_amd_gpio *variant_early_gpio_table(size_t *size);
@@ -32,6 +33,9 @@ const struct soc_amd_gpio *variant_early_gpio_table(size_t *size);
 /* This function provides GPIO settings at the end of bootblock. */
 const struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size);
 
+/* This function provides GPIO settings before PCIe enumeration. */
+const struct soc_amd_gpio *variant_pcie_gpio_table(size_t *size);
+
 /* This function provides GPIO settings before entering sleep. */
 const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size);
 
diff --git a/src/mainboard/google/guybrush/variants/guybrush/Makefile.inc b/src/mainboard/google/guybrush/variants/guybrush/Makefile.inc
index 8255ba8ebff3..f7c97bafbf46 100644
--- a/src/mainboard/google/guybrush/variants/guybrush/Makefile.inc
+++ b/src/mainboard/google/guybrush/variants/guybrush/Makefile.inc
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
 bootblock-y += gpio.c
+romstage-y += gpio.c
 ramstage-y += gpio.c
 
 subdirs-y += ./memory
diff --git a/src/mainboard/google/guybrush/variants/guybrush/gpio.c b/src/mainboard/google/guybrush/variants/guybrush/gpio.c
index e71ed9d57a6d..dca9c8edc7f8 100644
--- a/src/mainboard/google/guybrush/variants/guybrush/gpio.c
+++ b/src/mainboard/google/guybrush/variants/guybrush/gpio.c
@@ -25,6 +25,12 @@ static const struct soc_amd_gpio bid1_early_gpio_table[] = {
 	PAD_GPO(GPIO_70, HIGH),
 };
 
+/* This table is used by guybrush variant with board version < 2. */
+static const struct soc_amd_gpio bid1_pcie_gpio_table[] = {
+	/* SD_AUX_RESET_L */
+	PAD_GPO(GPIO_70, HIGH),
+};
+
 const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
 {
 	uint32_t board_version = board_id();
@@ -50,3 +56,16 @@ const struct soc_amd_gpio *variant_early_override_gpio_table(size_t *size)
 
 	return NULL;
 }
+
+const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size)
+{
+	uint32_t board_version = board_id();
+	*size = 0;
+
+	if (board_version < 2) {
+		*size = ARRAY_SIZE(bid1_pcie_gpio_table);
+		return bid1_pcie_gpio_table;
+	}
+
+	return NULL;
+}