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| author | Subrata Banik <subratabanik@google.com> | 2023-02-14 17:36:51 +0530 |
|---|---|---|
| committer | Eric Lai <eric_lai@quanta.corp-partner.google.com> | 2023-02-16 00:39:26 +0000 |
| commit | 45df1066ef2a9afe7e098410f0aa9a0440a6ea02 (patch) | |
| tree | 49c6de84b8abb8e7039d02aaa5dc62975d5d6bae /src/mainboard | |
| parent | 57987b6e195620aaa61499d4786a30ce2e924cae (diff) | |
| download | coreboot-45df1066ef2a9afe7e098410f0aa9a0440a6ea02.tar.gz coreboot-45df1066ef2a9afe7e098410f0aa9a0440a6ea02.tar.bz2 coreboot-45df1066ef2a9afe7e098410f0aa9a0440a6ea02.zip | |
mb/google/rex: Mark unused USB ports as empty
This patch marks unused USB ports (USB2.0/TCSS) empty to avoid
prompting wrong dmesg as below.
```
usb usb2-port3: Cannot enable. Maybe the USB cable is bad?
```
Mainboard variants to override the USB ports as per the target
board design.
TEST=Able to build and boot google/rex with all USB ports are
working as expected.
Change-Id: Ic3d21151a22f2318413f480f3386bf2dbf696307
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index d31cafc83a80..9a71e959c338 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -11,6 +11,25 @@ chip soc/intel/meteorlake # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" + register "usb2_ports[0]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 0 + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 1 + register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 2 + register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 3 + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 4 + register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 5 + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 6 + register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 7 + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 8 + register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 9 + + register "usb3_ports[0]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 0 + register "usb3_ports[1]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 1 + + register "tcss_ports[0]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 0 + register "tcss_ports[1]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 1 + register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 2 + register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 3 + # S0ix enable register "s0ix_enable" = "1" |