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| author | Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> | 2023-08-01 11:41:37 +0800 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2023-08-05 16:05:20 +0000 |
| commit | 4c68d8467af294b154281da7a0bbe5c9367e0885 (patch) | |
| tree | 5b71f457564a8dda2b4fc252805a83d331820d33 /src/mainboard | |
| parent | 1e67adbc73e30be098ce163e3d27a7a7ecf68ae0 (diff) | |
| download | coreboot-4c68d8467af294b154281da7a0bbe5c9367e0885.tar.gz coreboot-4c68d8467af294b154281da7a0bbe5c9367e0885.tar.bz2 coreboot-4c68d8467af294b154281da7a0bbe5c9367e0885.zip | |
mb/google/dedede/var/boxy: Add power limits for N4500/N5100
Add PLx from JSL PDG(ID: 613095) in boxy devicetree.
BUG=b:290293153
TEST=emerge-dedede coreboot and read correct value on boxy CPU log:
CPU TDP = 6 Watts, CPU PL4 = 60 Watts
Change-Id: I7b063dc235fb714ba47eb620b914f2f9e92a2715
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76876
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/dedede/variants/boxy/overridetree.cb | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/boxy/overridetree.cb b/src/mainboard/google/dedede/variants/boxy/overridetree.cb index ecf71aeaeaa8..10ae686a8cc9 100644 --- a/src/mainboard/google/dedede/variants/boxy/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boxy/overridetree.cb @@ -33,6 +33,19 @@ chip soc/intel/jasperlake }, }" + # Power limit config + register "power_limits_config[JSL_N4500_6W_CORE]" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 20, + .tdp_pl4 = 60, + }" + + register "power_limits_config[JSL_N5100_6W_CORE]" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 20, + .tdp_pl4 = 60, + }" + # Enable Root Port 3 (index 2) for LAN # External PCIe port 7 is mapped to PCIe Root Port 3 register "PcieRpEnable[2]" = "1" |