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| author | Lean Sheng Tan <lean.sheng.tan@intel.com> | 2021-06-09 06:51:22 -0700 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-06-30 07:35:32 +0000 |
| commit | 58ec51cc0aa3795d48b6d692a688017855d11baa (patch) | |
| tree | 18cbf62f45735681bce2da00960ec6d75841cf82 /src/mainboard | |
| parent | bed1b602d0cb6027c1b796cb1e44f335e56e0471 (diff) | |
| download | coreboot-58ec51cc0aa3795d48b6d692a688017855d11baa.tar.gz coreboot-58ec51cc0aa3795d48b6d692a688017855d11baa.tar.bz2 coreboot-58ec51cc0aa3795d48b6d692a688017855d11baa.zip | |
soc/intel/elkhartlake: Enable PCH GBE
Enable PCH GBE with following changes:
1. Configure PCH GBE related FSP UPD flags
2. Use EHL own GBE ACPI instead of common code version due to
different B:D.F from the usual GBE
3. Add kconfig PMC_EPOC to use the PMC XTAL read function
Due to EHL GBE comes with time sensitive networking (TSN)
capability integrated, EHL FSP is using 'PchTsn' instead of the
usual 'PchLan' naming convention across the board.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I6b0108e892064e804693a34e360034ae7dbee68f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb index d6dca6772bd9..7c1d48aa148f 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb @@ -140,6 +140,10 @@ chip soc/intel/elkhartlake [PchSerialIoIndexUART2] = 1, }" + # TSN GBE related UPDs + register "PchTsnGbeLinkSpeed" = "Tsn_2_5_Gbps" + register "PchTsnGbeSgmiiEnable" = "1" + # GPIO for SD card detect register "sdcard_cd_gpio" = "GPP_G5" |