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| author | Rex Chou <rex_chou@compal.corp-partner.google.com> | 2023-08-04 15:29:59 +0800 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2023-08-05 16:03:11 +0000 |
| commit | 684eca7dd2187346405180425d3537ed48db3c47 (patch) | |
| tree | 1db81029a650089496e5edd6bb901ea97b84f366 /src/mainboard | |
| parent | 8c77e58cd6a8caaf0c75916391d04e43e1a11aa9 (diff) | |
| download | coreboot-684eca7dd2187346405180425d3537ed48db3c47.tar.gz coreboot-684eca7dd2187346405180425d3537ed48db3c47.tar.bz2 coreboot-684eca7dd2187346405180425d3537ed48db3c47.zip | |
mb/google/nissa/var/craaskov: Configure the external V1p05/Vnn/VnnSx
This patch configures external V1p05/Vnn/VnnSx rails for Craaskov
to follow best practices for power savings – untested though.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
S4, S5 , S0 states.
* Set the supported voltage states.
* Set the voltage for v1p05 and vnn.
* Set the ICC max for v1p05 and vnn.
BUG=b:290165011
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: Ibaf6a285788e26688d3d42691ab40052ef6d6cdb
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76926
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/brya/variants/craaskov/overridetree.cb | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/craaskov/overridetree.cb b/src/mainboard/google/brya/variants/craaskov/overridetree.cb index e78c978f235e..ca32cd5fee77 100644 --- a/src/mainboard/google/brya/variants/craaskov/overridetree.cb +++ b/src/mainboard/google/brya/variants/craaskov/overridetree.cb @@ -8,6 +8,21 @@ chip soc/intel/alderlake register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + # Configure external V1P05/Vnn/VnnSx Rails + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0, + .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, + .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX, + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE, + .v1p05_voltage_mv = 1050, + .vnn_voltage_mv = 780, + .vnn_sx_voltage_mv = 1050, + .v1p05_icc_max_ma = 500, + .vnn_icc_max_ma = 500, + }" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | |