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| author | Jamie Ryu <jamie.m.ryu@intel.com> | 2022-07-22 11:27:25 -0700 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-09-19 14:56:11 +0000 |
| commit | b6cce33b18a7eb5f3e19bff4f102ec18ef30435a (patch) | |
| tree | f5affb895a2f6bb38cc733519d1edbf5bb9efdaa /src/mainboard | |
| parent | 9f44a8cc39542906d2571e02fe2696ae11ded958 (diff) | |
| download | coreboot-b6cce33b18a7eb5f3e19bff4f102ec18ef30435a.tar.gz coreboot-b6cce33b18a7eb5f3e19bff4f102ec18ef30435a.tar.bz2 coreboot-b6cce33b18a7eb5f3e19bff4f102ec18ef30435a.zip | |
mb/intel/mtlrvp: Add flashmap descriptor
This adds 32MB flashmap descriptor as below:
Descriptor Region: 0x0 - 0x3fff (~16KB)
Intel EC Region: 0x4000 - 0x83fff (~512KB)
ME Region: 0x84000 - 0x8fffff (~8.5MB)
BIOS Region: 0x900000 - 0x01ffffff (~23MB)
BUG=b:224325352
TEST=util/abuild/abuild -p none -t intel/mtlrvp -a -c max
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: Ifb572efe56eb7400b8328ba797892738f5927158
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66098
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/intel/mtlrvp/chromeos.fmd | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/src/mainboard/intel/mtlrvp/chromeos.fmd b/src/mainboard/intel/mtlrvp/chromeos.fmd new file mode 100644 index 000000000000..9fc7d7b2c87b --- /dev/null +++ b/src/mainboard/intel/mtlrvp/chromeos.fmd @@ -0,0 +1,46 @@ +FLASH 32M { + SI_ALL 9M { + SI_DESC 16K + SI_EC 512K + SI_ME + } + SI_BIOS 23M { + RW_SECTION_A 6M { + VBLOCK_A 64K + FW_MAIN_A(CBFS) + RW_FWID_A 64 + ME_RW_A(CBFS) 3008K + } + RW_LEGACY(CBFS) 2M + RW_MISC 1M { + UNIFIED_MRC_CACHE 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 24K + } + RW_SECTION_B 6M { + VBLOCK_B 64K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + ME_RW_B(CBFS) 3008K + } + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO 8M { + RO_VPD(PRESERVE) 16K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 12K + COREBOOT(CBFS) + } + } + } +} |