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| author | Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> | 2021-07-24 18:00:44 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-07-28 17:09:55 +0000 |
| commit | c5ac6d9ec5689e50d9b501b7cfa752ac26486b2c (patch) | |
| tree | a44227c579761e0db4c5fe0988ddf73ba49d6ab5 /src/mainboard | |
| parent | ce227fe02d9695993e33403cd5eb3537c7bfff92 (diff) | |
| download | coreboot-c5ac6d9ec5689e50d9b501b7cfa752ac26486b2c.tar.gz coreboot-c5ac6d9ec5689e50d9b501b7cfa752ac26486b2c.tar.bz2 coreboot-c5ac6d9ec5689e50d9b501b7cfa752ac26486b2c.zip | |
mb/google/brya/variants/primus: Update NVMe clk
According to the schematic diagram of proto, modify the clock of nvme
from the baseboard default to src0.
BUG=b:194487277
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I41be517b434513bca2332ec37e54f56910302bb7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/brya/variants/primus/overridetree.cb | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb index 6464b8bcbf39..39aa77ea9a61 100644 --- a/src/mainboard/google/brya/variants/primus/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -176,6 +176,14 @@ chip soc/intel/alderlake device generic 0 on end end end #PCIE8 SD card + device ref pcie_rp9 on + # Enable NVMe PCIE 9 using clk 0 + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end #PCIE9-12 SSD device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" |