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authorEric Biederman <ebiederm@xmission.com>2003-07-19 04:28:22 +0000
committerEric Biederman <ebiederm@xmission.com>2003-07-19 04:28:22 +0000
commit9b4336cf418d22551bea09d93e1cee79281b110e (patch)
tree3f1e24216c11918644a98fd1e46e2fdb40fd12fe /src/northbridge/amd/amdk8/early_ht.c
parentfe4414587a4466b848184b8837d4c5a280949824 (diff)
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- Major cleanup of the bootpath
- Changes to allow more code to be compiled both ways - Working SMP support git-svn-id: svn://svn.coreboot.org/coreboot/trunk@987 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/amdk8/early_ht.c')
-rw-r--r--src/northbridge/amd/amdk8/early_ht.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/northbridge/amd/amdk8/early_ht.c b/src/northbridge/amd/amdk8/early_ht.c
index b8262d519c3f..4de8fa1075f0 100644
--- a/src/northbridge/amd/amdk8/early_ht.c
+++ b/src/northbridge/amd/amdk8/early_ht.c
@@ -1,11 +1,12 @@
-static void enumerate_ht_chain(void)
+static int enumerate_ht_chain(unsigned link)
{
/* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
* On most boards this just happens. If a cpu has multiple
* non Coherent links the appropriate bus registers for the
* links needs to be programed to point at bus 0.
*/
- unsigned next_unitid, last_unitid;;
+ unsigned next_unitid, last_unitid;
+ int reset_needed = 0;
next_unitid = 1;
do {
uint32_t id;
@@ -46,4 +47,5 @@ static void enumerate_ht_chain(void)
pos = pci_read_config8(PCI_DEV(0, 0, 0), pos + PCI_CAP_LIST_NEXT);
}
} while((last_unitid != next_unitid) && (next_unitid <= 0x1f));
+ return reset_needed;
}