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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-05-17 14:16:03 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-06-02 21:56:06 +0000 |
| commit | 4c0e277e4ea358f7a36a75b503def54578fcd536 (patch) | |
| tree | ca70cb5959a95d0cf5302c5ef1bbec248fe6f50f /src/northbridge/intel/e7505/e7505.h | |
| parent | 717b6e3151b6ea42aaa4b1ab2a708e143d098878 (diff) | |
| download | coreboot-4c0e277e4ea358f7a36a75b503def54578fcd536.tar.gz coreboot-4c0e277e4ea358f7a36a75b503def54578fcd536.tar.bz2 coreboot-4c0e277e4ea358f7a36a75b503def54578fcd536.zip | |
intel/e7505: Assume AGP slot disabled
Reducing two AGP aperture windows from default 256 MiB to
chipset minimum 4 MiB releases 504 MiB of unused MMIO space.
Thus we can decrease MMIO space reserve from 1024 MiB to 512 MiB.
Supported CPUs are 32-bit with PAE, so there is a little reason
to avoid overlarge MMIO region.
Change-Id: I34818e1ca36058309c7c5c295992ba6dda154acc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/e7505/e7505.h')
| -rw-r--r-- | src/northbridge/intel/e7505/e7505.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/northbridge/intel/e7505/e7505.h b/src/northbridge/intel/e7505/e7505.h index 9c9171d2bd85..5ceeacceafd2 100644 --- a/src/northbridge/intel/e7505/e7505.h +++ b/src/northbridge/intel/e7505/e7505.h @@ -42,6 +42,7 @@ #define DRC 0x7C /* DRAM Controller Mode register, 32 bit */ #define DRDCTL 0x80 /* DRAM Read Timing Control register, 16 bit? (if similar to 855PM) */ #define CKDIS 0x8C /* Clock disable register, 8 bit */ +#define APSIZE 0xB4 #define TOLM 0xC4 /* Top of Low Memory register, 16 bit */ #define REMAPBASE 0xC6 /* Remap Base Address register, 16 bit */ #define REMAPLIMIT 0xC8 /* Remap Limit Address register, 16 bit */ @@ -82,4 +83,8 @@ #define DRAM_FERR 0x80 /* DRAM first error register, 8 bits */ #define DRAM_NERR 0x82 /* DRAM next error register, 8 bits */ +/************ D1:F0 ************/ + +#define APSIZE1 0x74 + #endif /* NORTHBRIDGE_INTEL_E7505_E7505_H */ |