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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-01-18 04:25:48 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-11-28 10:05:28 +0000 |
| commit | 560c3f5ccfff0fc289bb46f1b1b6c4236817590a (patch) | |
| tree | 59906cc1926d7e643dd1ec95022c87228560f152 /src/northbridge/intel/e7505/northbridge.c | |
| parent | 0c745347d09e08d9cf388600558ea41634e5cbcd (diff) | |
| download | coreboot-560c3f5ccfff0fc289bb46f1b1b6c4236817590a.tar.gz coreboot-560c3f5ccfff0fc289bb46f1b1b6c4236817590a.tar.bz2 coreboot-560c3f5ccfff0fc289bb46f1b1b6c4236817590a.zip | |
aopen/dxplplusu: Support SMM_ASEG and SMM_TSEG
Both SMM_ASEG and SMM_TSEG choices work.
There is periodic TCO timeout occurring.
At least with DEBUG_SMI kernel reports low memory corruption.
Change-Id: If20a7092117612a1a9e25eb6ac480e105acd57d7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/e7505/northbridge.c')
| -rw-r--r-- | src/northbridge/intel/e7505/northbridge.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 08ac12224310..cc7f85d98024 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -42,6 +42,9 @@ static void mch_domain_read_resources(struct device *dev) ram_resource_kb(dev, idx++, 0, tolmk); mmio_resource_kb(dev, idx++, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB); + uintptr_t tseg_memory_base = northbridge_get_tseg_base(); + size_t tseg_memory_size = northbridge_get_tseg_size(); + mmio_resource_kb(dev, idx++, tseg_memory_base / KiB, tseg_memory_size / KiB); ASSERT(tom == remapbase); upper_ram_end(dev, idx++, remaplimit); |