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author | Arthur Heymans <arthur@aheymans.xyz> | 2018-01-24 23:25:13 +0100 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2018-03-28 06:49:19 +0000 |
commit | 8b76605a4af9b45894c39cd7b9c480bd96f523cd (patch) | |
tree | 4d24a5aa80b7e6e1b19ef62868fc442aa1a8c128 /src/northbridge/intel/gm45/gm45.h | |
parent | a050817ce57ef960bf2bec3a18f23b59039dd184 (diff) | |
download | coreboot-8b76605a4af9b45894c39cd7b9c480bd96f523cd.tar.gz coreboot-8b76605a4af9b45894c39cd7b9c480bd96f523cd.tar.bz2 coreboot-8b76605a4af9b45894c39cd7b9c480bd96f523cd.zip |
nb/intel/gm45: Allocate a 8M TSEG region
Tested on Thinkpad X200.
Change-Id: I9db7a71608aaec956a7b22649498b97d58f35265
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23418
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/gm45/gm45.h')
-rw-r--r-- | src/northbridge/intel/gm45/gm45.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 34f734c5cbe3..df9c449e248d 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -433,6 +433,7 @@ void gm45_late_init(stepping_t); u32 decode_igd_memory_size(u32 gms); u32 decode_igd_gtt_size(u32 gsm); +u32 decode_tseg_size(u8 esmramc); void init_iommu(void); |