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| author | Stefan Reinauer <reinauer@chromium.org> | 2013-03-19 13:46:03 -0700 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-20 04:16:11 +0100 |
| commit | 2c3f16182523dbfd7b2ba490a93698377232ce57 (patch) | |
| tree | 0e6d30c10b6177cc62c2c4781891bca72912f91d /src/northbridge/intel/haswell/acpi/haswell.asl | |
| parent | 511c4b7f638a0f22761b135a42cba0a57fdb5e8f (diff) | |
| download | coreboot-2c3f16182523dbfd7b2ba490a93698377232ce57.tar.gz coreboot-2c3f16182523dbfd7b2ba490a93698377232ce57.tar.bz2 coreboot-2c3f16182523dbfd7b2ba490a93698377232ce57.zip | |
Intel: Update CPU microcode for Sandybridge/Ivybridge CPUs
Using the CPU microcode update script and
Intel's Linux* Processor Microcode Data File
from 2013-02-22
Change-Id: I853e381240b539b204c653404ca3d46369109219
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2846
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge/intel/haswell/acpi/haswell.asl')
0 files changed, 0 insertions, 0 deletions