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| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-25 12:56:29 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-11-04 22:02:46 +0000 |
| commit | c5381e0f36b49356e965b9f82c5dbe66dc660a86 (patch) | |
| tree | 6fcc1bbd73cca836644111c9fc3e04a838ebe637 /src/northbridge/intel/haswell/acpi/haswell.asl | |
| parent | 47276639312e742076c2f731c92727f31c26da35 (diff) | |
| download | coreboot-c5381e0f36b49356e965b9f82c5dbe66dc660a86.tar.gz coreboot-c5381e0f36b49356e965b9f82c5dbe66dc660a86.tar.bz2 coreboot-c5381e0f36b49356e965b9f82c5dbe66dc660a86.zip | |
nb/intel/haswell/acpi: Align with Broadwell
Align cosmetics and move CTDP-specific ASL into its own file.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change.
Change-Id: I476a4e01016caa3658177b0fa8916576f4a5e0e5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46755
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/haswell/acpi/haswell.asl')
| -rw-r--r-- | src/northbridge/intel/haswell/acpi/haswell.asl | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl index 4a9debfd3e27..57344abc1d4b 100644 --- a/src/northbridge/intel/haswell/acpi/haswell.asl +++ b/src/northbridge/intel/haswell/acpi/haswell.asl @@ -8,28 +8,28 @@ /* PCI Device Resource Consumption */ Device (PDRC) { - Name (_HID, EISAID("PNP0C02")) + Name (_HID, EISAID ("PNP0C02")) Name (_UID, 1) - Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) - Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000) - Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) - Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) - Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) - Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH - Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH - Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH + Name (PDRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, DEFAULT_RCBA, 0x00004000) + Memory32Fixed (ReadWrite, DEFAULT_MCHBAR, 0x00008000) + Memory32Fixed (ReadWrite, DEFAULT_DMIBAR, 0x00001000) + Memory32Fixed (ReadWrite, DEFAULT_EPBAR, 0x00001000) + Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) + Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // Misc ICH + Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // Misc ICH + Memory32Fixed (ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH #if CONFIG(CHROMEOS_RAMOOPS) - Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START, - CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE) + Memory32Fixed (ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START, + CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE) #endif }) // Current Resource Settings Method (_CRS, 0, Serialized) { - Return(PDRS) + Return (PDRS) } } |