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| author | Stefan Reinauer <stepan@coresystems.de> | 2009-07-21 21:44:24 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2009-07-21 21:44:24 +0000 |
| commit | 71a3d96bc487f66c84ac869a1215b8a4a4499bf2 (patch) | |
| tree | 97704a40b61a3e8d1f40e3bd0f972b86182cbdaa /src/northbridge/intel/i945/acpi/i945.asl | |
| parent | 4da810bd53f3e47fe0c5de64b5cec0910237a022 (diff) | |
| download | coreboot-71a3d96bc487f66c84ac869a1215b8a4a4499bf2.tar.gz coreboot-71a3d96bc487f66c84ac869a1215b8a4a4499bf2.tar.bz2 coreboot-71a3d96bc487f66c84ac869a1215b8a4a4499bf2.zip | |
* drop ich7 include
* detect more i945 variants
* raminit fixes
* ACPI + PCIe updates
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4455 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel/i945/acpi/i945.asl')
| -rw-r--r-- | src/northbridge/intel/i945/acpi/i945.asl | 51 |
1 files changed, 33 insertions, 18 deletions
diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl index e6ba95d00dcd..49986f9cef8d 100644 --- a/src/northbridge/intel/i945/acpi/i945.asl +++ b/src/northbridge/intel/i945/acpi/i945.asl @@ -26,35 +26,50 @@ Device (PDRC) { Name (_HID, EISAID("PNP0C02")) Name (_UID, 1) + + // This does not seem to work correctly yet - set values statically for + // now. + + //Name (PDRS, ResourceTemplate() { + // Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, RCRB) // RCBA + // Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, MCHB) // MCHBAR + // Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, DMIB) // DMIBAR + // Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, EGPB) // EPBAR + // Memory32Fixed(ReadWrite, 0x00000000, 0x00000000, PCIE) // PCIE BAR + // Memory32Fixed(ReadWrite, 0xfed20000, 0x00070000, ICHB) // Misc ICH + //}) + Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, RCRB) // RCBA - Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, MCHB) // MCHBAR - Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, DMIB) // DMIBAR - Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, EGPB) // EPBAR - Memory32Fixed(ReadWrite, 0x00000000, 0x00000000, PCIE) // PCIE BAR - Memory32Fixed(ReadWrite, 0xfed20000, 0x00070000, ICHB) // Misc ICH + Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA + Memory32Fixed(ReadWrite, 0xfed14000, 0x00004000) // MCHBAR + Memory32Fixed(ReadWrite, 0xfed18000, 0x00001000) // DMIBAR + Memory32Fixed(ReadWrite, 0xfed19000, 0x00001000) // EPBAR + Memory32Fixed(ReadWrite, 0xf0000000, 0x04000000) // PCIE BAR + Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH + Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH + Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH }) // Current Resource Settings Method (_CRS, 0, Serialized) { - CreateDwordField(PDRS, ^RCRB._BAS, RBR0) - ShiftLeft(\_SB.PCI0.LPCB.RCBA, 14, RBR0) + //CreateDwordField(PDRS, ^RCRB._BAS, RBR0) + //ShiftLeft(\_SB.PCI0.LPCB.RCBA, 14, RBR0) - CreateDwordField(PDRS, ^MCHB._BAS, MBR0) - ShiftLeft(\_SB.PCI0.MCHC.MHBR, 14, MBR0) + //CreateDwordField(PDRS, ^MCHB._BAS, MBR0) + //ShiftLeft(\_SB.PCI0.MCHC.MHBR, 14, MBR0) - CreateDwordField(PDRS, ^DMIB._BAS, DBR0) - ShiftLeft(\_SB.PCI0.MCHC.DMBR, 12, DBR0) + //CreateDwordField(PDRS, ^DMIB._BAS, DBR0) + //ShiftLeft(\_SB.PCI0.MCHC.DMBR, 12, DBR0) - CreateDwordField(PDRS, ^EGPB._BAS, EBR0) - ShiftLeft(\_SB.PCI0.MCHC.EPBR, 12, EBR0) + //CreateDwordField(PDRS, ^EGPB._BAS, EBR0) + //ShiftLeft(\_SB.PCI0.MCHC.EPBR, 12, EBR0) - CreateDwordField(PDRS, ^PCIE._BAS, PBR0) - ShiftLeft(\_SB.PCI0.MCHC.PXBR, 26, PBR0) + //CreateDwordField(PDRS, ^PCIE._BAS, PBR0) + //ShiftLeft(\_SB.PCI0.MCHC.PXBR, 26, PBR0) - CreateDwordField(PDRS, ^PCIE._LEN, PSZ0) - ShiftLeft(0x10000000, \_SB.PCI0.MCHC.PXSZ, PSZ0) + //CreateDwordField(PDRS, ^PCIE._LEN, PSZ0) + //ShiftLeft(0x10000000, \_SB.PCI0.MCHC.PXSZ, PSZ0) Return(PDRS) } |