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authorAngel Pons <th3fanbus@gmail.com>2020-06-11 14:13:33 +0200
committerFelix Held <felix-coreboot@felixheld.de>2020-07-22 14:51:39 +0000
commit3580d816e6d7a08434d91e9e1acdb94a47f07836 (patch)
tree05f09f89f19c110c9c05078eb82852d160f0af5b /src/northbridge/intel/i945/i945.h
parentce55b36c999a0d7c9e47418f81df4566a813670d (diff)
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nb/intel/i945: Put names to northbridge PCI devices
Tested with BUILD_TIMELESS=1, Getac P470 does not change. Change-Id: I0d51f48f0c1e37c41322a0eda49806925d9d194d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42285 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/i945/i945.h')
-rw-r--r--src/northbridge/intel/i945/i945.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index 20558b31cb8d..5275d1bfb74b 100644
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -31,6 +31,7 @@
#define INT15_5F35_CL_DISPLAY_LCD2 (1 << 7)
/* Device 0:0.0 PCI configuration space (Host Bridge) */
+#define HOST_BRIDGE PCI_DEV(0, 0, 0)
#define EPBAR 0x40
#define MCHBAR 0x44
@@ -88,6 +89,7 @@
/* Device 0:2.0 PCI configuration space (Graphics Device) */
+#define IGD_DEV PCI_DEV(0, 2, 0)
#define GMADR 0x18
#define GTTADR 0x1c